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1. 发明申请

US20110250726A1 SEMICONDUCTOR DEVICE HAVING A HETERO-JUNCTION BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有异质结双极晶体管的半导体器件及其制造方法
公开(公告)号：US20110250726A1
公开(公告)日：2011-10-13
申请号：US13165889
申请日：2011-06-22
申请人： Keiichi MURAYAMA , Akiyoshi TAMURA , Kenichi MIYAJIMA
发明人： Keiichi MURAYAMA , Akiyoshi TAMURA , Kenichi MIYAJIMA
IPC分类号： H01L21/8248
CPC分类号： H01L27/0605 , H01L21/8249 , H01L21/8252 , H01L27/0623
摘要： Method for manufacturing a semiconductor device. A channel layer is formed by epitaxially growing a semiconductor layer, in which an ion species of a first conductivity is implanted on a semiconductor substrate. A source region, a drain region, and an emitter region which are of the first conductivity, are formed by activating, using annealing, a portion of the semiconductor substrate in which the ion species has been implanted. An emitter layer of the first conductivity, a base layer of a second conductivity having a band gap smaller than a band gap of the emitter layer, and a collector layer of the first conductivity or a non-doped collector layer are sequentially and epitaxially grown on the channel layer.
摘要翻译：半导体器件的制造方法通过外延生长半导体层形成沟道层，其中第一导电性的离子种类被注入到半导体衬底上。通过使用退火激活已经注入了离子种的半导体衬底的一部分来形成具有第一导电性的源极区，漏极区和发射极区。第一导电性的发射极层，具有小于发射极层的带隙的带隙的第二导电性的基底层和第一导电性或非掺杂的集电极层的集电极层依次并外延生长在通道层。

2. 发明申请

US20100187571A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100187571A1
公开(公告)日：2010-07-29
申请号：US12690296
申请日：2010-01-20
申请人： Kenichi MIYAJIMA , Akiyoshi TAMURA , Keiichi MURAYAMA
发明人： Kenichi MIYAJIMA , Akiyoshi TAMURA , Keiichi MURAYAMA
IPC分类号： H01L29/08 , H01L21/8222
CPC分类号： H01L29/7371 , H01L21/8252 , H01L27/0605 , H01L29/205 , H01L29/207 , H01L29/66242 , H01L29/66462 , H01L29/7783
摘要： An object of the present invention is to provide a semiconductor resistive element having excellent linearity. A semiconductor device according to the present invention includes a HBT which is formed on a GaAs substrate and includes a group III-V compound semiconductor, and a semiconductor resistive element made of at least one layer included in a semiconductor epitaxial layer included in the HBT, and the semiconductor resistive element includes helium impurities.
摘要翻译：本发明的目的是提供具有优异线性的半导体电阻元件。根据本发明的半导体器件包括HBT，其形成在GaAs衬底上并且包括III-V族化合物半导体，以及由包括在HBT中的包括在半导体外延层中的至少一层制成的半导体电阻元件，并且半导体电阻元件包括氦杂质。

3. 发明申请

US20090230431A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090230431A1
公开(公告)日：2009-09-17
申请号：US12400376
申请日：2009-03-09
申请人： Keiichi MURAYAMA , Akiyoshi TAMURA , Hirotaka MIYAMOTO , Kenichi MIYAJIMA
发明人： Keiichi MURAYAMA , Akiyoshi TAMURA , Hirotaka MIYAMOTO , Kenichi MIYAJIMA
IPC分类号： H01L27/06 , H01L21/331
CPC分类号： H01L27/0623 , H01L21/8248 , H01L27/0605 , H01L29/7371 , H01L29/802
摘要： The present invention has as an objective to provide: a semiconductor device to satisfy both of the trade-off characteristic advantages of the HBT; and the HFET and a manufacturing method thereof. The semiconductor device in the present invention is an HBT and HFET integrated circuit. The HBT includes a sub-collector layer, a GaAs collector layer, a GaAs base layer, and an InGaP emitter layer which are sequentially stacked. The sub-collector layer includes a GaAs external sub-collector region, and a GaAs internal sub-collector region disposed on the GaAs external sub-collector region. A mesa-shaped collector part and a collector electrode are separately formed on the GaAs external sub-collector region. The HFET includes a GaAs cap layer, a source electrode, and a drain electrode, the GaAs cap layer including portion of the GaAs external sub-collector region, and the source electrode and the drain electrode being formed on the GaAs cap layer.
摘要翻译：本发明的目的是提供一种半导体装置，以满足HBT的两个折衷特征优点; 和HFET及其制造方法。本发明的半导体器件是HBT和HFET集成电路。 HBT包括依次层叠的副集电极层，GaAs集电极层，GaAs基极层和InGaP发射极层。子集电极层包括GaAs外部副集电极区域和设置在GaAs外部子集电极区域上的GaAs内部子集电极区域。在GaAs外部副集电极区域上分别形成台状集电体部和集电极。 HFET包括GaAs覆盖层，源电极和漏电极，GaAs覆盖层包括GaAs外部副集电极区域的一部分，源电极和漏电极形成在GaAs覆盖层上。

4. 发明授权

US07176098B2 Semiconductor element and method for fabricating the same 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US07176098B2
公开(公告)日：2007-02-13
申请号：US11062851
申请日：2005-02-23
申请人： Keisuke Kojima , Toshiharu Tanbo , Keiichi Murayama
发明人： Keisuke Kojima , Toshiharu Tanbo , Keiichi Murayama
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/7371 , H01L29/0817 , H01L29/66318
摘要： A heterojunction bipolar transistor comprises a collector layer, a base layer formed on the collector layer and an emitter layer formed on the base layer. The emitter layer includes a first semiconductor layer covering the entire top surface of the base layer and a second semiconductor layer formed on a predetermined part of the first semiconductor layer. An inactivated region is formed, by ion implantation, in a region of the collector layer located below the base layer except for a part thereof corresponding to the second semiconductor layer. The edge of the inactivated region is located away from the edge of the second semiconductor layer, and a region of the first semiconductor layer between the edge of the inactivated region and the edge of the second semiconductor layer is depleted.
摘要翻译：异质结双极晶体管包括集电极层，形成在集电极层上的基极层和形成在基极层上的发射极层。发射极层包括覆盖基底层的整个顶表面的第一半导体层和形成在第一半导体层的预定部分上的第二半导体层。通过离子注入在位于基底层下方的除了与第二半导体层相对应的部分之外的集电极层的区域中形成钝化区域。钝化区域的边缘位于远离第二半导体层的边缘的位置，并且在非活化区域的边缘和第二半导体层的边缘之间的第一半导体层的区域被耗尽。

5. 发明申请

US20050199909A1 Heterojunction bipolar transistor and manufacturing method thereof 有权
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US20050199909A1
公开(公告)日：2005-09-15
申请号：US10980254
申请日：2004-11-04
申请人： Keiichi Murayama , Yorito Ota , Akiyoshi Tamura
发明人： Keiichi Murayama , Yorito Ota , Akiyoshi Tamura
IPC分类号： H01L21/331 , H01L29/205 , H01L29/737 , H01L29/739
CPC分类号： H01L29/66318 , H01L29/0817 , H01L29/7371
摘要： The present invention aims at providing a heterojunction bipolar transistor having improved breakdown voltage on operation for high power output, and includes: a GaAs semiconductor substrate 100; an n+-type GaAs sub-collector layer 110; an n-type GaAs collector layer 120; a p-type GaAs base layer 130; an emitter layer 140; an n-type GaAs emitter cap layer 150; and an n-type InGaAs emitter contact layer 160. The emitter layer 140 has a multilayer structure including an n-type or non-doped first emitter layer 141 and an n-type second emitter layer 142 which are laminated in sequence. The first emitter layer 141 is made of a semiconductor material including Al, while the second emitter layer 142 is made of InxGa1-xP (0
摘要翻译：本发明的目的在于提供一种异质结双极晶体管，其具有在高功率输出操作时具有改进的击穿电压，并且包括：GaAs半导体衬底100; 一个n + +型GaAs子集电极层110; n型GaAs集电极层120; p型GaAs基极层130; 发射极层140; n型GaAs发射极帽层150; 和n型InGaAs发射极接触层160.发射极层140具有包括依次层叠的n型或非掺杂的第一发射极层141和n型第二发射极层142的多层结构。第一发射极层141由包括Al的半导体材料制成，而第二发射极层142由In x Ga 1-x P（0

6. 发明申请

US20050145884A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050145884A1
公开(公告)日：2005-07-07
申请号：US10902120
申请日：2004-07-30
申请人： Masanobu Nogome , Akiyoshi Tamura , Keiichi Murayama
发明人： Masanobu Nogome , Akiyoshi Tamura , Keiichi Murayama
IPC分类号： H01L21/331 , H01L29/737 , H01L29/739
CPC分类号： H01L29/7371 , H01L29/0821
摘要： It is the object of the present invention to provide a semiconductor device having an improved breakdown voltage on high power output, the semiconductor device comprising a n-type GaAs subcollector layer 101, a n-type GaAs intermediate collector layer 102 formed between a collector layer 103 and the subcollector layer 101, the n-type GaAs collector layer 103, a p-type GaAs base layer 104, a n-type InGaP second emitter layer 105, a n-type GaAs first emitter layer 106, and a n-type InGaAs emitter contact layer 107, and a concentration of impurities in the intermediate collector layer 102 is higher than a concentration of impurities in the collector layer 103 and is lower than a concentration of impurities in the subcollector layer 101.
摘要翻译：本发明的目的是提供一种在高功率输出上具有改进的击穿电压的半导体器件，该半导体器件包括n型GaAs子集电极层101，n型GaAs中间集电极层102，其形成在集电极层 103和子集电极层101，n型GaAs集电极层103，p型GaAs基极层104，n型InGaP第二发射极层105，n型GaAs第一发射极层106和n型 InGaAs发射极接触层107，并且中间集电极层102中的杂质浓度高于集电极层103中的杂质浓度，并且低于子集电极层101中的杂质浓度。

7. 发明申请

US20050078081A1 Liquid crystal display device 审中-公开
标题翻译：液晶显示装置
公开(公告)号：US20050078081A1
公开(公告)日：2005-04-14
申请号：US10981640
申请日：2004-11-05
申请人： Kyoichiro Oda , Akimasa Yuuki , Shin Tahata , Toshio Tobita , Shiro Miyake , Kazuhiro Kobayashi , Keiichi Murayama
发明人： Kyoichiro Oda , Akimasa Yuuki , Shin Tahata , Toshio Tobita , Shiro Miyake , Kazuhiro Kobayashi , Keiichi Murayama
IPC分类号： G02F1/13357 , G02F1/133 , G09G3/20 , G09G3/34 , G09G3/36 , H04N5/66
CPC分类号： G09G3/342 , G09G3/2011 , G09G3/3648 , G09G2310/0224 , G09G2310/024 , G09G2310/061 , G09G2310/08 , G09G2320/0252 , G09G2320/0261 , G09G2320/0285 , G09G2320/041 , G09G2320/0633 , G09G2320/064 , G09G2340/16
摘要： A liquid crystal display device comprising a including signal correcting means correction for correcting a level of an original image signal to a level with which transmittance in a steady state of the pixel with the original image signal is attained within one frame period, a horizontal driving means for driver applying a voltage in correspondence with the corrected image signal to a liquid crystal material, and an illumination device for illuminating the display panel with a plurality of light emitting regions thereof, said the light emitting regions sequentially turns turning on and off in synchronization with the application of the corrected image signal, while holding a definite time delay thereto.
摘要翻译：一种液晶显示装置，包括：信号校正装置校正装置，用于将原始图像信号的电平校正到在一个帧周期内获得具有原始图像信号的像素的稳定状态下的透射率的水平;水平驱动装置驱动器将对应于校正图像信号的电压施加到液晶材料，以及照明装置，用于以多个发光区域照亮显示面板，所述发光区域顺序地与校正图像信号的应用，同时保持一定的时间延迟。

8. 发明授权

US07989845B2 Semiconductor device having a hetero-junction bipolar transistor and manufacturing method thereof 有权
标题翻译：具有异质结双极晶体管的半导体器件及其制造方法
公开(公告)号：US07989845B2
公开(公告)日：2011-08-02
申请号：US12126395
申请日：2008-05-23
申请人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
发明人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
IPC分类号： H01L31/0328
CPC分类号： H01L27/0605 , H01L21/8249 , H01L21/8252 , H01L27/0623
摘要： The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of a semiconductor substrate; and an HFET formed on a second region of the semiconductor substrate, wherein the HBT includes: an emitter layer of a first conductivity; a base layer of a second conductivity that has a band gap smaller than that of the emitter layer; a collector layer of the first conductivity or a non-doped collector layer; and a sub-collector layer of the first conductivity which are formed sequentially on the first region, and the HFET includes an electron donor layer including a part of the emitter layer, and a channel layer formed under the electron donor layer.
摘要翻译：本发明的目的是提供一种能够防止集电极击穿电压降低并且集电极电阻降低的半导体器件及其制造方法。根据本发明的半导体器件包括：形成在半导体衬底的第一区域上的HBT; 以及形成在所述半导体衬底的第二区域上的HFET，其中所述HBT包括：具有第一导电性的发射极层; 具有比发射极层的带隙小的带隙的第二导电性的基底层; 第一电导率的集电极层或非掺杂集电极层; 以及在第一区域上依次形成的第一导电性的副集电极层，并且HFET包括包含发射极层的一部分的电子供体层和形成在电子供体层下面的沟道层。

9. 发明授权

US07566920B2 Bipolar transistor and power amplifier 有权
标题翻译：双极晶体管和功率放大器
公开(公告)号：US07566920B2
公开(公告)日：2009-07-28
申请号：US11484753
申请日：2006-07-12
申请人： Katsuhiko Kawashima , Masahiro Maeda , Keiichi Murayama , Hirotaka Miyamoto
发明人： Katsuhiko Kawashima , Masahiro Maeda , Keiichi Murayama , Hirotaka Miyamoto
IPC分类号： H01L29/737
CPC分类号： H01L29/7371 , H01L29/0692 , H01L29/41708 , H01L29/42304 , H01L29/66318
摘要： A base mesa finger (an emitter ledge layer 15, a base layer 16, and a collector layer 17) is interposed between two collector fingers (collector electrodes 13), and on the base mesa finger, a base finger (a base electrode 12) and two emitter fingers (an emitter layer 14 and an emitter electrode 11) on both sides of the base finger, are formed. The two emitter fingers are formed symmetric with respect to the base finger as a reference.
摘要翻译：基底台面（发射极壁缘层15，基底层16和集电体层17）介于两个集电极指（集电极13）之间，并且在基底台面上指基底指（基底电极12）并且形成在基指的两侧上的两个发射极指（发射极层14和发射极11）。两个发射极指相对于基指形成对称的基准。

10. 发明申请

US20060132241A1 Transistor integrated circuit device and manufacturing method thereof 审中-公开
标题翻译：晶体管集成电路器件及其制造方法
公开(公告)号：US20060132241A1
公开(公告)日：2006-06-22
申请号：US10545786
申请日：2004-10-08
申请人： Katsuhiko Kawashima , Masahiro Maeda , Keiichi Murayama , Hirotaka Miyamoto
发明人： Katsuhiko Kawashima , Masahiro Maeda , Keiichi Murayama , Hirotaka Miyamoto
IPC分类号： H03F3/191
CPC分类号： H01L27/0629 , H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： There are provided a transistor integrated circuit device which reduces the integrated area of a circuit while avoiding an element destruction caused by thermal runaway, and a method of manufacturing the transistor integrated circuit device. A cut capacitor (13) is composed of an upper electrode formed from a wiring metal and in a first layer; and a lower electrode formed from a wiring metal and in a second layer. A bias resistor (12) is formed from the same wiring metal as that of the lower electrode of the cut capacitor (13). This bias resistor (12) is formed from a wiring metal which is made into a thin film to function as a sheet resistor, and the resistance value of the bias resistor (12) can be freely set according to the thickness or width of the wiring metal.
摘要翻译：提供了一种晶体管集成电路器件，其减少了电路的集成面积，同时避免了由热失控引起的元件损坏，以及制造晶体管集成电路器件的方法。切断电容器（13）由由布线金属形成的上电极和第一层构成; 以及由布线金属和第二层形成的下电极。偏置电阻器（12）由与切断电容器（13）的下电极相同的布线金属形成。该偏置电阻器（12）由布线金属形成，该布线金属制成薄膜以用作片状电阻器，并且可以根据布线的厚度或宽度自由设置偏置电阻器（12）的电阻值金属。

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