专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07566920B2 Bipolar transistor and power amplifier 有权
标题翻译：双极晶体管和功率放大器
公开(公告)号：US07566920B2
公开(公告)日：2009-07-28
申请号：US11484753
申请日：2006-07-12
申请人： Katsuhiko Kawashima , Masahiro Maeda , Keiichi Murayama , Hirotaka Miyamoto
发明人： Katsuhiko Kawashima , Masahiro Maeda , Keiichi Murayama , Hirotaka Miyamoto
IPC分类号： H01L29/737
CPC分类号： H01L29/7371 , H01L29/0692 , H01L29/41708 , H01L29/42304 , H01L29/66318
摘要： A base mesa finger (an emitter ledge layer 15, a base layer 16, and a collector layer 17) is interposed between two collector fingers (collector electrodes 13), and on the base mesa finger, a base finger (a base electrode 12) and two emitter fingers (an emitter layer 14 and an emitter electrode 11) on both sides of the base finger, are formed. The two emitter fingers are formed symmetric with respect to the base finger as a reference.
摘要翻译：基底台面（发射极壁缘层15，基底层16和集电体层17）介于两个集电极指（集电极13）之间，并且在基底台面上指基底指（基底电极12）并且形成在基指的两侧上的两个发射极指（发射极层14和发射极11）。两个发射极指相对于基指形成对称的基准。

2. 发明申请

US20060132241A1 Transistor integrated circuit device and manufacturing method thereof 审中-公开
标题翻译：晶体管集成电路器件及其制造方法
公开(公告)号：US20060132241A1
公开(公告)日：2006-06-22
申请号：US10545786
申请日：2004-10-08
申请人： Katsuhiko Kawashima , Masahiro Maeda , Keiichi Murayama , Hirotaka Miyamoto
发明人： Katsuhiko Kawashima , Masahiro Maeda , Keiichi Murayama , Hirotaka Miyamoto
IPC分类号： H03F3/191
CPC分类号： H01L27/0629 , H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： There are provided a transistor integrated circuit device which reduces the integrated area of a circuit while avoiding an element destruction caused by thermal runaway, and a method of manufacturing the transistor integrated circuit device. A cut capacitor (13) is composed of an upper electrode formed from a wiring metal and in a first layer; and a lower electrode formed from a wiring metal and in a second layer. A bias resistor (12) is formed from the same wiring metal as that of the lower electrode of the cut capacitor (13). This bias resistor (12) is formed from a wiring metal which is made into a thin film to function as a sheet resistor, and the resistance value of the bias resistor (12) can be freely set according to the thickness or width of the wiring metal.
摘要翻译：提供了一种晶体管集成电路器件，其减少了电路的集成面积，同时避免了由热失控引起的元件损坏，以及制造晶体管集成电路器件的方法。切断电容器（13）由由布线金属形成的上电极和第一层构成; 以及由布线金属和第二层形成的下电极。偏置电阻器（12）由与切断电容器（13）的下电极相同的布线金属形成。该偏置电阻器（12）由布线金属形成，该布线金属制成薄膜以用作片状电阻器，并且可以根据布线的厚度或宽度自由设置偏置电阻器（12）的电阻值金属。

3. 发明申请

US20070012949A1 Bipolar transistor and power amplifier 有权
标题翻译：双极晶体管和功率放大器
公开(公告)号：US20070012949A1
公开(公告)日：2007-01-18
申请号：US11484753
申请日：2006-07-12
申请人： Katsuhiko Kawashima , Masahiro Maeda , Keiichi Murayama , Hirotaka Miyamoto
发明人： Katsuhiko Kawashima , Masahiro Maeda , Keiichi Murayama , Hirotaka Miyamoto
IPC分类号： H01L31/00 , H01L21/336
CPC分类号： H01L29/7371 , H01L29/0692 , H01L29/41708 , H01L29/42304 , H01L29/66318
摘要： A base mesa finger (an emitter ledge layer 15, a base layer 16, and a collector layer 17) is interposed between two collector fingers (collector electrodes 13), and on the base mesa finger, a base finger (a base electrode 12) and two emitter fingers (an emitter layer 14 and an emitter electrode 11) on both sides of the base finger, are formed. The two emitter fingers are formed symmetric with respect to the base finger as a reference.
摘要翻译：基底台面（发射极壁缘层15，基底层16和集电体层17）介于两个集电极指（集电极13）之间，并且在基底台面上指基底指（基底电极12）并且形成在基指的两侧上的两个发射极指（发射极层14和发射极11）。两个发射极指相对于基指形成对称的基准。

4. 发明授权

US07728357B2 Heterojunction bipolar transistor and manufacturing method thereof 有权
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US07728357B2
公开(公告)日：2010-06-01
申请号：US11614113
申请日：2006-12-21
申请人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
发明人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
IPC分类号： H01L29/739
CPC分类号： H01L29/7371 , H01L29/0821 , H01L29/66318
摘要： The object of the present invention is to provide a heterojunction bipolar transistor with high breakdown tolerance which can be manufactured at a high reproducibility and a high yield, the heterojunction bipolar transistor includes: a sub-collector layer; a collector layer formed on the sub-collector layer; a base layer formed on the collector layer; and an emitter layer, which is formed on the base layer and is made of a semiconductor that has a larger bandgap than a semiconductor of the base layer, in which the collector layer includes: a first collector layer formed on the sub-collector layer; a second collector layer formed on the first collector layer; and a third collector layer formed between the second collector layer and the base layer, a semiconductor of the first collector layer differs from semiconductors of the third collector layer and the second collector layer, and an impurity concentration of the second collector layer is lower than an impurity concentration of the sub-collector layer and higher than an impurity concentration of the third collector layer.
摘要翻译：本发明的目的是提供一种能够以高再现性和高产率制造的具有高击穿耐受性的异质结双极晶体管，该异质结双极晶体管包括：亚集电极层; 形成在所述副集电极层上的集电体层; 形成在集电体层上的基层; 以及发射极层，其形成在所述基底层上并且由具有比所述基底层的半导体更大的带隙的半导体形成，所述集电极层包括：形成在所述副集电极层上的第一集电体层; 形成在所述第一集电体层上的第二集电体层; 以及形成在所述第二集电体层和所述基极层之间的第三集电体层，所述第一集电体层的半导体与所述第三集电体层和所述第二集电体层的半导体不同，所述第二集电体层的杂质浓度低于副集电极层的杂质浓度高于第三集电体层的杂质浓度。

5. 发明授权

US07989845B2 Semiconductor device having a hetero-junction bipolar transistor and manufacturing method thereof 有权
标题翻译：具有异质结双极晶体管的半导体器件及其制造方法
公开(公告)号：US07989845B2
公开(公告)日：2011-08-02
申请号：US12126395
申请日：2008-05-23
申请人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
发明人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
IPC分类号： H01L31/0328
CPC分类号： H01L27/0605 , H01L21/8249 , H01L21/8252 , H01L27/0623
摘要： The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of a semiconductor substrate; and an HFET formed on a second region of the semiconductor substrate, wherein the HBT includes: an emitter layer of a first conductivity; a base layer of a second conductivity that has a band gap smaller than that of the emitter layer; a collector layer of the first conductivity or a non-doped collector layer; and a sub-collector layer of the first conductivity which are formed sequentially on the first region, and the HFET includes an electron donor layer including a part of the emitter layer, and a channel layer formed under the electron donor layer.
摘要翻译：本发明的目的是提供一种能够防止集电极击穿电压降低并且集电极电阻降低的半导体器件及其制造方法。根据本发明的半导体器件包括：形成在半导体衬底的第一区域上的HBT; 以及形成在所述半导体衬底的第二区域上的HFET，其中所述HBT包括：具有第一导电性的发射极层; 具有比发射极层的带隙小的带隙的第二导电性的基底层; 第一电导率的集电极层或非掺杂集电极层; 以及在第一区域上依次形成的第一导电性的副集电极层，并且HFET包括包含发射极层的一部分的电子供体层和形成在电子供体层下面的沟道层。

6. 发明授权

US08017975B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08017975B2
公开(公告)日：2011-09-13
申请号：US12400376
申请日：2009-03-09
申请人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
发明人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
IPC分类号： H01L29/66
CPC分类号： H01L27/0623 , H01L21/8248 , H01L27/0605 , H01L29/7371 , H01L29/802
摘要： A semiconductor device and manufacturing method satisfies both of the trade-off characteristic advantages of the HBT and the HFET. The semiconductor device is an HBT and HFET integrated circuit. The HBT includes a sub-collector layer, a GaAs collector layer, a GaAs base layer, and an InGaP emitter layer that are sequentially stacked. The sub-collector layer includes a GaAs external sub-collector region, and a GaAs internal sub-collector region disposed on the GaAs external sub-collector region. A mesa-shaped collector part and a collector electrode are separately formed on the GaAs external sub-collector region. The HFET includes a GaAs cap layer, a source electrode, and a drain electrode. The GaAs cap layer includes a portion of the GaAs external sub-collector region. The source electrode and the drain electrode are formed on the GaAs cap layer.
摘要翻译：半导体器件和制造方法满足HBT和HFET两者的折衷特性优点。该半导体器件是HBT和HFET集成电路。 HBT包括依次堆叠的子集电极层，GaAs集电极层，GaAs基极层和InGaP发射极层。子集电极层包括GaAs外部副集电极区域和设置在GaAs外部子集电极区域上的GaAs内部子集电极区域。在GaAs外部副集电极区域上分别形成台状集电体部和集电极。 HFET包括GaAs覆盖层，源电极和漏电极。 GaAs覆盖层包括GaAs外部副集电极区域的一部分。源电极和漏极形成在GaAs盖层上。

7. 发明授权

US07449729B2 Heterojunction bipolar transistor and method for fabricating the same 失效
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US07449729B2
公开(公告)日：2008-11-11
申请号：US11398599
申请日：2006-04-06
申请人： Kenichi Miyajima , Keiichi Murayama , Hirotaka Miyamoto
发明人： Kenichi Miyajima , Keiichi Murayama , Hirotaka Miyamoto
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/7371 , H01L29/66318
摘要： On a high-concentration n-type first sub-collector layer, a high-concentration n-type second sub-collector layer made of a material having a small bandgap, an i-type or low-concentration n-type collector layer, a high-concentration p-type base layer, an n-type emitter layer made of a material having a large bandgap, a high-concentration n-type emitter cap layer, a high-concentration n-type emitter contact layer made of a material having a small bandgap are sequentially stacked. From the emitter contact layer, an interconnection also serving as an emitter electrode is extended. From the emitter layer or the base layer, an interconnection also serving as a base electrode is extended. From the second sub-collector layer, an interconnection also serving as a collector electrode is extended.
摘要翻译：在高浓度n型第一副集电极层上，由具有小带隙，i型或低浓度n型集电极层的材料制成的高浓度n型第二子集电极层，高浓度p型基底层，由具有大带隙的材料制成的n型发射极层，高浓度n型发射极帽层，由具有高浓度p型基底层的材料制成的高浓度n型发射极接触层，依次层叠小带隙。从发射极接触层，扩展了也用作发射极的互连。从发射极层或基极层延伸也用作基极的互连。从第二子集电极层延伸也用作集电极的互连。

8. 发明申请

US20060289896A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060289896A1
公开(公告)日：2006-12-28
申请号：US11348378
申请日：2006-02-07
申请人： Hirotaka Miyamoto , Keiichi Murayama , Kenichi Miyajima
发明人： Hirotaka Miyamoto , Keiichi Murayama , Kenichi Miyajima
IPC分类号： H01L31/00
CPC分类号： H01L29/7371 , H01L23/485 , H01L23/647 , H01L25/072 , H01L29/41708 , H01L29/42304 , H01L29/66318 , H01L29/7304 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device has an interconnect layer for providing an electric connection between a base electrode and a base terminal provided on the region of a semi-insulating substrate on which a transistor is not formed. A resistor layer composed of a material different from respective materials composing the base electrode and the interconnect layer is formed on the base electrode and the base electrode and the interconnect layer are connected to each other via the resistor layer.
摘要翻译：半导体器件具有互连层，用于在未形成晶体管的半绝缘基板的区域上提供基极和基极之间的电连接。在基极上形成由不同于构成基极的材料和互连层的材料构成的电阻层，并且基极和布线层经由电阻层彼此连接。

9. 发明申请

US20060237743A1 Heterojunction bipolar transistor and method for fabricating the same 失效
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US20060237743A1
公开(公告)日：2006-10-26
申请号：US11398599
申请日：2006-04-06
申请人： Kenichi Miyajima , Keiichi Murayama , Hirotaka Miyamoto
发明人： Kenichi Miyajima , Keiichi Murayama , Hirotaka Miyamoto
IPC分类号： H01L29/732
CPC分类号： H01L29/7371 , H01L29/66318
摘要： On a high-concentration n-type first sub-collector layer, a high-concentration n-type second sub-collector layer made of a material having a small bandgap, an i-type or low-concentration n-type collector layer, a high-concentration p-type base layer, an n-type emitter layer made of a material having a large bandgap, a high-concentration n-type emitter cap layer, a high-concentration n-type emitter contact layer made of a material having a small bandgap are sequentially stacked. From the emitter contact layer, an interconnection also serving as an emitter electrode is extended. From the emitter layer or the base layer, an interconnection also serving as a base electrode is extended. From the second sub-collector layer, an interconnection also serving as a collector electrode is extended.
摘要翻译：在高浓度n型第一副集电极层上，由具有小带隙，i型或低浓度n型集电极层的材料制成的高浓度n型第二子集电极层，高浓度p型基底层，由具有大带隙的材料制成的n型发射极层，高浓度n型发射极帽层，由具有高浓度p型基底层的材料制成的高浓度n型发射极接触层，依次层叠小带隙。从发射极接触层，扩展了也用作发射极的互连。从发射极层或基极层延伸也用作基极的互连。从第二子集电极层延伸也用作集电极的互连。

10. 发明授权

US07176098B2 Semiconductor element and method for fabricating the same 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US07176098B2
公开(公告)日：2007-02-13
申请号：US11062851
申请日：2005-02-23
申请人： Keisuke Kojima , Toshiharu Tanbo , Keiichi Murayama
发明人： Keisuke Kojima , Toshiharu Tanbo , Keiichi Murayama
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/7371 , H01L29/0817 , H01L29/66318
摘要： A heterojunction bipolar transistor comprises a collector layer, a base layer formed on the collector layer and an emitter layer formed on the base layer. The emitter layer includes a first semiconductor layer covering the entire top surface of the base layer and a second semiconductor layer formed on a predetermined part of the first semiconductor layer. An inactivated region is formed, by ion implantation, in a region of the collector layer located below the base layer except for a part thereof corresponding to the second semiconductor layer. The edge of the inactivated region is located away from the edge of the second semiconductor layer, and a region of the first semiconductor layer between the edge of the inactivated region and the edge of the second semiconductor layer is depleted.
摘要翻译：异质结双极晶体管包括集电极层，形成在集电极层上的基极层和形成在基极层上的发射极层。发射极层包括覆盖基底层的整个顶表面的第一半导体层和形成在第一半导体层的预定部分上的第二半导体层。通过离子注入在位于基底层下方的除了与第二半导体层相对应的部分之外的集电极层的区域中形成钝化区域。钝化区域的边缘位于远离第二半导体层的边缘的位置，并且在非活化区域的边缘和第二半导体层的边缘之间的第一半导体层的区域被耗尽。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式