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1. 发明授权

US08017975B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08017975B2
公开(公告)日：2011-09-13
申请号：US12400376
申请日：2009-03-09
申请人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
发明人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
IPC分类号： H01L29/66
CPC分类号： H01L27/0623 , H01L21/8248 , H01L27/0605 , H01L29/7371 , H01L29/802
摘要： A semiconductor device and manufacturing method satisfies both of the trade-off characteristic advantages of the HBT and the HFET. The semiconductor device is an HBT and HFET integrated circuit. The HBT includes a sub-collector layer, a GaAs collector layer, a GaAs base layer, and an InGaP emitter layer that are sequentially stacked. The sub-collector layer includes a GaAs external sub-collector region, and a GaAs internal sub-collector region disposed on the GaAs external sub-collector region. A mesa-shaped collector part and a collector electrode are separately formed on the GaAs external sub-collector region. The HFET includes a GaAs cap layer, a source electrode, and a drain electrode. The GaAs cap layer includes a portion of the GaAs external sub-collector region. The source electrode and the drain electrode are formed on the GaAs cap layer.
摘要翻译：半导体器件和制造方法满足HBT和HFET两者的折衷特性优点。该半导体器件是HBT和HFET集成电路。 HBT包括依次堆叠的子集电极层，GaAs集电极层，GaAs基极层和InGaP发射极层。子集电极层包括GaAs外部副集电极区域和设置在GaAs外部子集电极区域上的GaAs内部子集电极区域。在GaAs外部副集电极区域上分别形成台状集电体部和集电极。 HFET包括GaAs覆盖层，源电极和漏电极。 GaAs覆盖层包括GaAs外部副集电极区域的一部分。源电极和漏极形成在GaAs盖层上。

2. 发明授权

US07989845B2 Semiconductor device having a hetero-junction bipolar transistor and manufacturing method thereof 有权
标题翻译：具有异质结双极晶体管的半导体器件及其制造方法
公开(公告)号：US07989845B2
公开(公告)日：2011-08-02
申请号：US12126395
申请日：2008-05-23
申请人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
发明人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
IPC分类号： H01L31/0328
CPC分类号： H01L27/0605 , H01L21/8249 , H01L21/8252 , H01L27/0623
摘要： The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of a semiconductor substrate; and an HFET formed on a second region of the semiconductor substrate, wherein the HBT includes: an emitter layer of a first conductivity; a base layer of a second conductivity that has a band gap smaller than that of the emitter layer; a collector layer of the first conductivity or a non-doped collector layer; and a sub-collector layer of the first conductivity which are formed sequentially on the first region, and the HFET includes an electron donor layer including a part of the emitter layer, and a channel layer formed under the electron donor layer.
摘要翻译：本发明的目的是提供一种能够防止集电极击穿电压降低并且集电极电阻降低的半导体器件及其制造方法。根据本发明的半导体器件包括：形成在半导体衬底的第一区域上的HBT; 以及形成在所述半导体衬底的第二区域上的HFET，其中所述HBT包括：具有第一导电性的发射极层; 具有比发射极层的带隙小的带隙的第二导电性的基底层; 第一电导率的集电极层或非掺杂集电极层; 以及在第一区域上依次形成的第一导电性的副集电极层，并且HFET包括包含发射极层的一部分的电子供体层和形成在电子供体层下面的沟道层。

3. 发明授权

US07728357B2 Heterojunction bipolar transistor and manufacturing method thereof 有权
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US07728357B2
公开(公告)日：2010-06-01
申请号：US11614113
申请日：2006-12-21
申请人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
发明人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
IPC分类号： H01L29/739
CPC分类号： H01L29/7371 , H01L29/0821 , H01L29/66318
摘要： The object of the present invention is to provide a heterojunction bipolar transistor with high breakdown tolerance which can be manufactured at a high reproducibility and a high yield, the heterojunction bipolar transistor includes: a sub-collector layer; a collector layer formed on the sub-collector layer; a base layer formed on the collector layer; and an emitter layer, which is formed on the base layer and is made of a semiconductor that has a larger bandgap than a semiconductor of the base layer, in which the collector layer includes: a first collector layer formed on the sub-collector layer; a second collector layer formed on the first collector layer; and a third collector layer formed between the second collector layer and the base layer, a semiconductor of the first collector layer differs from semiconductors of the third collector layer and the second collector layer, and an impurity concentration of the second collector layer is lower than an impurity concentration of the sub-collector layer and higher than an impurity concentration of the third collector layer.
摘要翻译：本发明的目的是提供一种能够以高再现性和高产率制造的具有高击穿耐受性的异质结双极晶体管，该异质结双极晶体管包括：亚集电极层; 形成在所述副集电极层上的集电体层; 形成在集电体层上的基层; 以及发射极层，其形成在所述基底层上并且由具有比所述基底层的半导体更大的带隙的半导体形成，所述集电极层包括：形成在所述副集电极层上的第一集电体层; 形成在所述第一集电体层上的第二集电体层; 以及形成在所述第二集电体层和所述基极层之间的第三集电体层，所述第一集电体层的半导体与所述第三集电体层和所述第二集电体层的半导体不同，所述第二集电体层的杂质浓度低于副集电极层的杂质浓度高于第三集电体层的杂质浓度。

4. 发明授权

US07001820B1 Heterojunction bipolar transistor and method for fabricating the same 失效
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US07001820B1
公开(公告)日：2006-02-21
申请号：US11066220
申请日：2005-02-28
申请人： Kenichi Miyajima , Akiyoshi Tamura , Keiichi Murayama
发明人： Kenichi Miyajima , Akiyoshi Tamura , Keiichi Murayama
IPC分类号： H01L21/331
CPC分类号： H01L29/66318 , H01L29/7371
摘要： The following layers are successively formed on a heavily-doped n-type first subcollector layer: a heavily-doped n-type second subcollector layer made of a material having a small band gap; an i-type or a lightly-doped n-type collector layer; a heavily-doped p-type base layer; an n-type emitter layer made of a material having a large band gap; a heavily-doped n-type emitter cap layer; and a heavily-doped n-type emitter contact layer made of a material having a small band gap. Alloying reaction layers are formed under an emitter electrode, a base electrode and a collector electrode.
摘要翻译：在重掺杂n型第一子集电极层上依次形成以下层：由具有小带隙的材料制成的重掺杂n型第二子集电极层; i型或轻掺杂的n型集电极层; 重掺杂p型基层; 由具有大带隙的材料制成的n型发射极层; 重掺杂的n型发射极盖层; 以及由具有小带隙的材料制成的重掺杂n型发射极接触层。合金反应层形成在发射电极，基极和集电极之下。

5. 发明申请

US20060030113A1 HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：异相双极晶体管及其制造方法
公开(公告)号：US20060030113A1
公开(公告)日：2006-02-09
申请号：US11066220
申请日：2005-02-28
申请人： Kenichi Miyajima , Akiyoshi Tamura , Keiichi Murayama
发明人： Kenichi Miyajima , Akiyoshi Tamura , Keiichi Murayama
IPC分类号： H01L21/331
CPC分类号： H01L29/66318 , H01L29/7371
摘要： The following layers are successively formed on a heavily-doped n-type first subcollector layer: a heavily-doped n-type second subcollector layer made of a material having a small band gap; an i-type or a lightly-doped n-type collector layer; a heavily-doped p-type base layer; an n-type emitter layer made of a material having a large band gap; a heavily-doped n-type emitter cap layer; and a heavily-doped n-type emitter contact layer made of a material having a small band gap. Alloying reaction layers are formed under an emitter electrode, a base electrode and a collector electrode.
摘要翻译：在重掺杂n型第一子集电极层上依次形成以下层：由具有小带隙的材料制成的重掺杂n型第二子集电极层; i型或轻掺杂的n型集电极层; 重掺杂p型基层; 由具有大带隙的材料制成的n型发射极层; 重掺杂的n型发射极盖层; 以及由具有小带隙的材料制成的重掺杂n型发射极接触层。合金反应层形成在发射电极，基极和集电极之下。

6. 发明授权

US07176099B2 Hetero-junction bipolar transistor and manufacturing method thereof 有权
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US07176099B2
公开(公告)日：2007-02-13
申请号：US11100511
申请日：2005-04-07
申请人： Keiichi Murayama , Akiyoshi Tamura , Masanobu Nogome
发明人： Keiichi Murayama , Akiyoshi Tamura , Masanobu Nogome
IPC分类号： H01L21/8222
CPC分类号： H01L29/0821 , H01L29/7371
摘要： A hetero-junction bipolar transistor that satisfies high resistance required to avoid a potential breakdown includes: an n-type sub-collector layer 110 that is made of GaAs; an n-type first collector 121 that is made of a semiconductor material with a smaller avalanche coefficient than that of the sub-collector 110 and is formed on the sub-collector layer 110; a second collector layer 132 that is made of n-type or i-type GaAs with lower dopant concentration than that of the sub-collector layer 110 and is formed on the first collector layer 121; a p-type base layer 133 that is made of GaAs and is formed on the second collector layer 132; and emitter layer 134 that is made of a semiconductor material with a larger band gap than that of the base layer 133 and is formed on the base layer 133.
摘要翻译：满足避免电位击穿所需的高电阻的异质结双极晶体管包括：由GaAs制成的n型子集电极层110; 形成在副集电极层110上的由具有比亚集电体110的雪崩系数小的半导体材料制成的n型第一集电体121; 第二集电体层132由n型或i型GaAs制成，掺杂浓度低于副集电极层110的掺杂浓度，并形成在第一集电极层121上; 由GaAs制成并形成在第二集电层132上的p型基极层133; 以及由具有比基极层133的带隙大的带隙的半导体材料制成并且形成在基极层133上的发射极层134。

7. 发明授权

US07091528B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07091528B2
公开(公告)日：2006-08-15
申请号：US10902120
申请日：2004-07-30
申请人： Masanobu Nogome , Akiyoshi Tamura , Keiichi Murayama
发明人： Masanobu Nogome , Akiyoshi Tamura , Keiichi Murayama
IPC分类号： H01L31/328
CPC分类号： H01L29/7371 , H01L29/0821
摘要： A semiconductor device is provided having an improved breakdown voltage on high power output, the semiconductor device comprising a n-type GaAs subcollector layer, a n-type GaAs intermediate collector layer formed between a collector layer and the subcollector layer, the n-type GaAs collector layer, a p-type GaAs base layer, a n-type InGaP second emitter layer, a n-type GaAs first emitter layer, and a n-type InGaAs emitter contact layer, and a concentration of impurities in the intermediate collector layer is higher than a concentration of impurities in the collector layer and is lower than a concentration of impurities in the subcollector layer.
摘要翻译：提供了一种在高功率输出上具有改进的击穿电压的半导体器件，该半导体器件包括n型GaAs子集电极层，形成在集电极层和子集电极层之间的n型GaAs中间集电极层，n型GaAs 集电极层，p型GaAs基极层，n型InGaP第二发射极层，n型GaAs第一发射极层和n型InGaAs发射极接触层，中间集电极层中的杂质浓度为高于集电体层中的杂质浓度，并且低于子集电极层中的杂质浓度。

8. 发明授权

US06982141B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06982141B2
公开(公告)日：2006-01-03
申请号：US10937366
申请日：2004-09-10
申请人： Masanobu Nogome , Akiyoshi Tamura , Keiichi Murayama , Kazutsune Miyanaga , Yoshitaka Kuroishi
发明人： Masanobu Nogome , Akiyoshi Tamura , Keiichi Murayama , Kazutsune Miyanaga , Yoshitaka Kuroishi
IPC分类号： G03F7/00
CPC分类号： H01L21/76898 , H01L21/8252 , H01L23/481 , H01L27/0605 , H01L2924/0002 , Y10S430/136 , H01L2924/00
摘要： A GaAs substrate 200 is rotated, a photosensitive silicone resist 260 is applied on a surface of the GaAs substrate 200 on which an aperture of a hole 310 to be a via hole, and an inside of the hole 310 to be the via hole is filled in with the photosensitive silicone resist 260. Next, the GaAs substrate 200 is further rotated, changing the number of revolutions (rpm), and the photosensitive silicone resist 260 on the GaAs substrate is flattened. Next, a reverse side of the GaAs substrate is grinded, the hole 310 to be the via hole penetrates the GaAs substrate 200 from the surface to the reverse side and the via hole 220 is formed. Next, a reverse side electrode 240 is formed on the reverse side of the GaAs substrate 200. Next, the GaAs sustrate 200 is divided chip by chip and chips are laid on a substrate for assembly 270 via an adhesive metal 280.
摘要翻译：在GaAs衬底200旋转的同时，在GaAs衬底200的表面上施加感光性硅氧烷抗蚀剂260，在该衬底200的表面上填充孔310作为通孔的孔，填充孔310的内部与感光性硅氧烷抗蚀剂260接触。接着，进一步旋转GaAs衬底200，改变转速（rpm），使GaAs衬底上的感光性硅氧烷抗蚀剂260变平。接下来，研磨GaAs衬底的反面，作为通路孔的孔310从表面向反面侧穿过GaAs衬底200，形成通路孔220。接下来，在GaAs衬底200的相反侧上形成反向侧电极240.接下来，将GaAs衬垫200逐个分割，并且通过粘合金属280将芯片放置在用于组件270的衬底上。

9. 发明申请

US20050199910A1 Hetero-junction bipolar transistor and manufacturing method thereof 有权
公开(公告)号：US20050199910A1
公开(公告)日：2005-09-15
申请号：US11100511
申请日：2005-04-07
申请人： Keiichi Murayama , Akiyoshi Tamura , Masanobu Nogome
发明人： Keiichi Murayama , Akiyoshi Tamura , Masanobu Nogome
IPC分类号： H01L21/331 , H01L29/08 , H01L29/737 , H01L29/739 , H01L31/0328
CPC分类号： H01L29/0821 , H01L29/7371
摘要： A hetero-junction bipolar transistor that satisfies high resistance required to avoid a potential breakdown includes: an n-type sub-collector layer 110 that is made of GaAs; an n-type first collector 121 that is made of a semiconductor material with a smaller avalanche coefficient than that of the sub-collector 110 and is formed on the sub-collector layer 110; a second collector layer 132 that is made of n-type or i-type GaAs with lower dopant concentration than that of the sub-collector layer 110 and is formed on the first collector layer 121; a p-type base layer 133 that is made of GaAs and is formed on the second collector layer 132; and emitter layer 134 that is made of a semiconductor material with a larger band gap than that of the base layer 133 and is formed on the base layer 133.

10. 发明授权

US07301181B2 Heterojunction bipolar transistor having an emitter layer made of a semiconductor material including aluminum 有权
标题翻译：异质结双极晶体管具有由包括铝的半导体材料制成的发射极层
公开(公告)号：US07301181B2
公开(公告)日：2007-11-27
申请号：US10980254
申请日：2004-11-04
申请人： Keiichi Murayama , Yorito Ota , Akiyoshi Tamura
发明人： Keiichi Murayama , Yorito Ota , Akiyoshi Tamura
IPC分类号： H01L31/0328
CPC分类号： H01L29/66318 , H01L29/0817 , H01L29/7371
摘要： The present invention aims at providing a heterojunction bipolar transistor having improved breakdown voltage on operation for high power output, and includes: a GaAs semiconductor substrate 100; an n+-type GaAs sub-collector layer 110; an n-type GaAs collector layer 120; a p-type GaAs base layer 130; an emitter layer 140; an n-type GaAs emitter cap layer 150; and an n-type InGaAs emitter contact layer 160. The emitter layer 140 has a multilayer structure including an n-type or non-doped first emitter layer 141 and an n-type second emitter layer 142 which are laminated in sequence. The first emitter layer 141 is made of a semiconductor material including Al, while the second emitter layer 142 is made of InxGa1-xP (0
摘要翻译：本发明的目的在于提供一种异质结双极晶体管，其具有在高功率输出操作时具有改进的击穿电压，并且包括：GaAs半导体衬底100; 一个n + +型GaAs子集电极层110; n型GaAs集电极层120; p型GaAs基极层130; 发射极层140; n型GaAs发射极帽层150; 和n型InGaAs发射极接触层160.发射极层140具有包括依次层叠的n型或非掺杂的第一发射极层141和n型第二发射极层142的多层结构。第一发射极层141由包括Al的半导体材料制成，而第二发射极层142由In x Ga 1-x P（0

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