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1. 发明授权

US08169018B2 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US08169018B2
公开(公告)日：2012-05-01
申请号：US12713736
申请日：2010-02-26
申请人： Jang-hyun You , Jin-taek Park , Young-woo Park , Jung-dal Choi
发明人： Jang-hyun You , Jin-taek Park , Young-woo Park , Jung-dal Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11565 , H01L27/11573 , H01L29/4234
摘要： A non-volatile memory device includes a semiconductor layer including a cell region and a peripheral region, a cell region gate structure disposed in the cell region of the semiconductor layer, and wherein the cell region gate structure includes a tunneling insulating layer and a first blocking insulating layer, a second blocking insulating layer, and a third blocking insulating layer. The no-volatile memory device further includes a peripheral region gate structure formed in the peripheral region of the semiconductor layer. The peripheral region gate structure includes a first peripheral region insulating layer including a same material as a material included in the tunneling insulating layer and a second peripheral region insulating layer including a same material as a material included in the third blocking insulating layer.
摘要翻译：非易失性存储器件包括包括单元区域和外围区域的半导体层，设置在半导体层的单元区域中的单元区域栅极结构，并且其中单元区域栅极结构包括隧道绝缘层和第一阻挡层绝缘层，第二阻挡绝缘层和第三阻挡绝缘层。非易失性存储器件还包括形成在半导体层的周边区域中的外围区域栅极结构。周边区域栅极结构包括：第一周边区域绝缘层，其包括与包含在隧道绝缘层中的材料相同的材料;以及第二周边区域绝缘层，其包括与包含在第三阻挡绝缘层中的材料相同的材料。

2. 发明申请

US20110316165A1 Semiconductor Device and Method of Fabricating the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110316165A1
公开(公告)日：2011-12-29
申请号：US12912744
申请日：2010-10-27
申请人： JANG-HYUN YOU , JONG-MIN LEE , DONG-HWA KWAK , TAE-YONG KIM , JONG-HOON NA , YOUNG-WOO PARK , DONG-SIK LEE , JEE-HOON HAN
发明人： JANG-HYUN YOU , JONG-MIN LEE , DONG-HWA KWAK , TAE-YONG KIM , JONG-HOON NA , YOUNG-WOO PARK , DONG-SIK LEE , JEE-HOON HAN
IPC分类号： H01L23/538 , H01L21/768
CPC分类号： H01L21/0337 , H01L21/28273 , H01L21/3086 , H01L21/32139 , H01L21/76229 , H01L27/11521 , H01L27/11536 , H01L29/66825
摘要： A semiconductor device includes first, second, and third conductive lines, each with a respective line portion formed over a substrate and extending in a first direction and with a respective branch portion extending from an end of the respective line portion in a direction different from the first direction. The branch portion of a middle conductive line is disposed between and shorter than the respective branch portions of the outer conductive lines such that contact pads may be formed integral with such branch portions of the conductive lines.
摘要翻译：半导体器件包括第一，第二和第三导线，每个导线具有形成在衬底上并且沿第一方向延伸的相应的线部分，并且具有相应的分支部分，该分支部分从相应线部分的端部沿与第一个方向中间导线的分支部分设置在外导电线的相应分支部分之间并且短于接触焊盘可以与导电线的这种分支部分一体形成。

3. 发明授权

US07999307B2 Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
标题翻译：具有单元和外围区域的非易失性存储器件及其制造方法
公开(公告)号：US07999307B2
公开(公告)日：2011-08-16
申请号：US12923998
申请日：2010-10-20
申请人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
发明人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.
摘要翻译：提供了一种非易失性存储器件及其制造方法。存储单元可以设置在单元区域中，其中每个存储单元具有包括隧道绝缘层，浮动陷阱层和阻挡层的绝缘结构，以及包括能量阻挡层，阻挡金属层和低电阻的导电结构栅电极。可以使用具有较低电阻率的材料作为栅电极，以避免与电阻增加相关的问题，并允许栅电极相对较薄。存储器件还可以包括在外围区域中的晶体管，其可以具有栅极电介质层，多晶硅的下部栅电极和由金属硅化物制成的上部栅电极，从而允许与下部栅电极的改善的界面而不扩散或同时提供较低的电阻。

4. 发明授权

US07842997B2 Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
标题翻译：具有单元和外围区域的非易失性存储器件及其制造方法
公开(公告)号：US07842997B2
公开(公告)日：2010-11-30
申请号：US12078143
申请日：2008-03-27
申请人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
发明人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.
摘要翻译：提供了一种非易失性存储器件及其制造方法。存储单元可以设置在单元区域中，其中每个存储单元具有包括隧道绝缘层，浮动陷阱层和阻挡层的绝缘结构，以及包括能量阻挡层，阻挡金属层和低电阻的导电结构栅电极。可以使用具有较低电阻率的材料作为栅电极，以避免与电阻增加相关的问题，并允许栅电极相对较薄。存储器件还可以包括在外围区域中的晶体管，其可以具有栅极电介质层，多晶硅的下部栅电极和由金属硅化物制成的上部栅电极，从而允许与下部栅电极的改善的界面而不扩散或同时提供较低的电阻。

5. 发明申请

US20170207232A1 MEMORY DEVICE 审中-公开
公开(公告)号：US20170207232A1
公开(公告)日：2017-07-20
申请号：US15295119
申请日：2016-10-17
申请人： Jang Hyun YOU , Jin Taek PARK , Taek Soo SHIN , Sung Yun LEE
发明人： Jang Hyun YOU , Jin Taek PARK , Taek Soo SHIN , Sung Yun LEE
IPC分类号： H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/11521 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/788 , H01L29/792
摘要： A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.

6. 发明申请

US20150340376A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150340376A1
公开(公告)日：2015-11-26
申请号：US14620770
申请日：2015-02-12
申请人： Jintaek PARK , Sunghoi HUR , Jang-Hyun YOU
发明人： Jintaek PARK , Sunghoi HUR , Jang-Hyun YOU
IPC分类号： H01L27/115 , H01L23/528
CPC分类号： H01L27/11582 , H01L23/528 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L2924/0002 , H01L2924/00
摘要： According to example embodiments, a three-dimensional semiconductor device including a substrate with cell and connection regions, gate electrodes stacked on the cell region, a vertical channel structure, pads, a dummy pillar, and first and second semiconductor patterns. The vertical channel structure penetrates the gate electrodes on a lowermost gate electrode and includes a first gate dielectric pattern. The pads extend from the gate electrodes and are stacked on the connection region. The dummy pillar penetrates some of the pads on a lowermost pad and includes a second gate dielectric pattern. The first semiconductor patterns are between the vertical channel structure and the substrate. The second semiconductor patterns are between the dummy pillar and the substrate. The first and second gate dielectric patterns may be on the first and second semiconductor patterns, respectively. The second gate dielectric pattern may cover a whole top surface of the second semiconductor pattern.
摘要翻译：根据示例性实施例，包括具有单元和连接区域的衬底，堆叠在单元区域上的栅电极，垂直沟道结构，焊盘，虚拟柱以及第一和第二半导体图案的三维半导体器件。垂直沟道结构穿透最下面的栅电极上的栅极，并且包括第一栅极电介质图案。焊盘从栅电极延伸并且堆叠在连接区域上。虚拟柱穿透最低垫上的一些焊盘并且包括第二栅极电介质图案。第一半导体图案在垂直沟道结构和衬底之间。第二半导体图案位于虚拟柱和衬底之间。第一和第二栅极电介质图案可以分别在第一和第二半导体图案上。第二栅极电介质图案可以覆盖第二半导体图案的整个顶表面。

7. 发明申请

US20120122297A1 METHOD OF FABRICATING A NONVOLATILE MEMORY DEVICE 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20120122297A1
公开(公告)日：2012-05-17
申请号：US13198157
申请日：2011-08-04
申请人： Jong-Hoon NA , Young-Woo Park , Dong-Hwa Kwak , Tae-Yong Kim , Jee-Hoon Han , Jang-Hyun You , Dong-Sik Lee , Su-Jin Park
发明人： Jong-Hoon NA , Young-Woo Park , Dong-Hwa Kwak , Tae-Yong Kim , Jee-Hoon Han , Jang-Hyun You , Dong-Sik Lee , Su-Jin Park
IPC分类号： H01L21/762
CPC分类号： H01L27/0207 , H01L21/28273 , H01L27/11 , H01L27/11519 , H01L27/11524
摘要： A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.
摘要翻译：一种制造非易失性存储器件的方法包括提供具有由多个沟槽限定的有源区的衬底，在具有多个沟槽的衬底上形成第一隔离层，在第一隔离层上形成牺牲层以填充沟槽，所述牺牲层包括填充所述沟槽的下部的第一区域和除所述下部以外的第二区域填充部分，去除所述牺牲层的所述第二区域，在所述第一隔离层上形成第二隔离层和在所述第一隔离层的所述第一区域牺牲层，通过去除牺牲层的第一区域在沟槽中形成气隙，以及在保持气隙的同时去除第一隔离层的一部分和第二隔离层的一部分。

8. 发明授权

US07872295B2 Method of making flash memory cells and peripheral circuits having STI, and flash memory devices and computer systems having the same 有权
标题翻译：制造具有STI的闪速存储器单元和外围电路的方法，以及具有该闪速存储器单元的闪速存储器单元和外围电路
公开(公告)号：US07872295B2
公开(公告)日：2011-01-18
申请号：US12367988
申请日：2009-02-09
申请人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
发明人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
IPC分类号： H01L29/94
CPC分类号： H01L27/11573 , H01L27/11526 , H01L27/11546 , H01L27/11592 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.
摘要翻译：集成电路包括闪存单元，以及包括低压晶体管（LVT）和高压晶体管（HVT））的外围电路。集成电路包括包含SiON，SiN或其它高k材料的隧道势垒层。隧道势垒层可以包括HVT的栅极电介质的一部分。隧道势垒层可以构成HVT的整个栅电介质。相应的隧道势垒层可以形成在浅沟槽隔离（STI）之间或之间。因此，可以提高驱动器芯片IC的制造效率。

9. 发明授权

US08753955B2 Methods of fabricating nonvolatile memory devices including voids between active regions and related devices 有权
标题翻译：制造包括有源区域和相关器件之间的空隙的非易失性存储器件的方法
公开(公告)号：US08753955B2
公开(公告)日：2014-06-17
申请号：US13300787
申请日：2011-11-21
申请人： Dong-Sik Lee , Jang-Hyun You , Jee-Hoon Han , Young-Woo Park , Sung-Hoi Hur , Sang-Ick Joo
发明人： Dong-Sik Lee , Jang-Hyun You , Jee-Hoon Han , Young-Woo Park , Sung-Hoi Hur , Sang-Ick Joo
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/76229 , H01L21/764
摘要： A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.
摘要翻译：制造非易失性存储器件的方法包括在衬底中形成限定器件隔离区域的衬底中的沟槽，并且其间的有源区域。沟槽和其间的有源区延伸到衬底的第一和第二器件区域。牺牲层形成在第一器件区域中的有源区之间的沟槽中，并且形成绝缘层以基本上填充第二器件区域中的有源区之间的沟槽。选择性地去除第一器件区域中的沟槽中的牺牲层的至少一部分，以限定沿着第一器件区域中的有源区之间的沟槽延伸的间隙区域，同时基本上将沟槽中的绝缘层保持在有源区在第二设备区域中。还讨论了相关的方法和设备。

10. 发明申请

US20110117713A1 METHOD OF MAKING FLASH MEMORY CELLS AND PERIPHERAL CIRCUITS HAVING STI, AND FLASH MEMORY DEVICES AND COMPUTER SYSTEMS HAVING THE SAME 失效
标题翻译：制造闪速存储器细胞的方法和具有STI的外围电路以及具有该闪存存储器的闪速存储器件和计算机系统
公开(公告)号：US20110117713A1
公开(公告)日：2011-05-19
申请号：US12979890
申请日：2010-12-28
申请人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
发明人： Jin-Taek Park , Young-Woo Park , Jang-Hyun You , Jung-Dal Choi
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L27/11573 , H01L27/11526 , H01L27/11546 , H01L27/11592 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.
摘要翻译：集成电路包括闪存单元，以及包括低压晶体管（LVT）和高压晶体管（HVT））的外围电路。集成电路包括包含SiON，SiN或其它高k材料的隧道势垒层。隧道势垒层可以包括HVT的栅极电介质的一部分。隧道势垒层可以构成HVT的整个栅电介质。相应的隧道势垒层可以形成在浅沟槽隔离（STI）之间或之间。因此，可以提高驱动器芯片IC的制造效率。

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