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1. 发明申请

US20110037118A1 Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
公开(公告)号：US20110037118A1
公开(公告)日：2011-02-17
申请号：US12923998
申请日：2010-10-20
申请人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
发明人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.

2. 发明申请

US20080237700A1 Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
标题翻译：具有单元和外围区域的非易失性存储器件及其制造方法
公开(公告)号：US20080237700A1
公开(公告)日：2008-10-02
申请号：US12078143
申请日：2008-03-27
申请人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
发明人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.
摘要翻译：提供了一种非易失性存储器件及其制造方法。存储单元可以设置在单元区域中，其中每个存储单元具有包括隧道绝缘层，浮动陷阱层和阻挡层的绝缘结构，以及包括能量阻挡层，阻挡金属层和低电阻的导电结构栅电极。可以使用具有较低电阻率的材料作为栅电极，以避免与电阻增加相关的问题，并允许栅电极相对较薄。存储器件还可以包括在外围区域中的晶体管，其可以具有栅极电介质层，多晶硅的下部栅电极和由金属硅化物制成的上部栅电极，从而允许与下部栅电极的改善的界面而不扩散或同时提供较低的电阻。

3. 发明授权

US07999307B2 Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
标题翻译：具有单元和外围区域的非易失性存储器件及其制造方法
公开(公告)号：US07999307B2
公开(公告)日：2011-08-16
申请号：US12923998
申请日：2010-10-20
申请人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
发明人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.
摘要翻译：提供了一种非易失性存储器件及其制造方法。存储单元可以设置在单元区域中，其中每个存储单元具有包括隧道绝缘层，浮动陷阱层和阻挡层的绝缘结构，以及包括能量阻挡层，阻挡金属层和低电阻的导电结构栅电极。可以使用具有较低电阻率的材料作为栅电极，以避免与电阻增加相关的问题，并允许栅电极相对较薄。存储器件还可以包括在外围区域中的晶体管，其可以具有栅极电介质层，多晶硅的下部栅电极和由金属硅化物制成的上部栅电极，从而允许与下部栅电极的改善的界面而不扩散或同时提供较低的电阻。

4. 发明授权

US07842997B2 Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
标题翻译：具有单元和外围区域的非易失性存储器件及其制造方法
公开(公告)号：US07842997B2
公开(公告)日：2010-11-30
申请号：US12078143
申请日：2008-03-27
申请人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
发明人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.
摘要翻译：提供了一种非易失性存储器件及其制造方法。存储单元可以设置在单元区域中，其中每个存储单元具有包括隧道绝缘层，浮动陷阱层和阻挡层的绝缘结构，以及包括能量阻挡层，阻挡金属层和低电阻的导电结构栅电极。可以使用具有较低电阻率的材料作为栅电极，以避免与电阻增加相关的问题，并允许栅电极相对较薄。存储器件还可以包括在外围区域中的晶体管，其可以具有栅极电介质层，多晶硅的下部栅电极和由金属硅化物制成的上部栅电极，从而允许与下部栅电极的改善的界面而不扩散或同时提供较低的电阻。

5. 发明授权

US08188532B2 Semiconductor device having a gate contact structure capable of reducing interfacial resistance 有权
标题翻译：具有能够降低界面电阻的栅极接触结构的半导体器件
公开(公告)号：US08188532B2
公开(公告)日：2012-05-29
申请号：US12856295
申请日：2010-08-13
申请人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
发明人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/823462 , H01L21/823475 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.
摘要翻译：半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的插塞使多晶硅层通过开口接触。

6. 发明申请

US20100133604A1 Semiconductor Devices Having Gate Structures with Conductive Patterns of Different Widths and Methods of Fabricating Such Devices 有权
标题翻译：具有具有不同宽度的导电图案的门结构的半导体器件和制造这种器件的方法
公开(公告)号：US20100133604A1
公开(公告)日：2010-06-03
申请号：US12622594
申请日：2009-11-20
申请人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
发明人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L29/4234
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括依次层叠在半导体衬底上的第一电介质图案，数据存储图案和第二电介质图案。在第二电介质图案上提供第一导电图案。具有比第一导电图案更大的宽度的第二导电图案设置在第一导电图案上。

7. 发明授权

US08643077B2 Non-volatile memory devices including blocking insulation patterns with sub-layers having different energy band gaps 有权
标题翻译：非易失性存储器件包括具有不同能带隙的子层的阻挡绝缘图案
公开(公告)号：US08643077B2
公开(公告)日：2014-02-04
申请号：US13305930
申请日：2011-11-29
申请人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
发明人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11517 , H01L27/11529 , H01L27/11563 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/42348 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7883
摘要： A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底和半导体衬底上的隔离层，其中隔离层限定半导体衬底的有源区。可以在半导体衬底的有源区上设置隧道绝缘层，并且可以在隧道绝缘层上设置电荷存储图案。可以在电荷存储图案上提供界面层图案，并且可以在界面层图案上提供阻挡绝缘图案。此外，块绝缘图案可以包括高k介电材料，并且界面层图案和阻挡绝缘图案可以包括不同的材料。可以在阻挡绝缘层上设置控制栅电极，使得阻挡绝缘图案位于界面层图案和控制栅电极之间。还讨论了相关方法。

8. 发明授权

US08089114B2 Non-volatile memory devices including blocking and interface patterns between charge storage patterns and control electrodes and related methods 有权
标题翻译：包括电荷存储模式和控制电极之间的阻塞和接口模式的非易失性存储器件及相关方法
公开(公告)号：US08089114B2
公开(公告)日：2012-01-03
申请号：US12266032
申请日：2008-11-06
申请人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
发明人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11517 , H01L27/11529 , H01L27/11563 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/42348 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7883
摘要： A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底和半导体衬底上的隔离层，其中隔离层限定半导体衬底的有源区。可以在半导体衬底的有源区上设置隧道绝缘层，并且可以在隧道绝缘层上设置电荷存储图案。可以在电荷存储图案上提供界面层图案，并且可以在界面层图案上提供阻挡绝缘图案。此外，块绝缘图案可以包括高k介电材料，并且界面层图案和阻挡绝缘图案可以包括不同的材料。可以在阻挡绝缘层上设置控制栅电极，使得阻挡绝缘图案位于界面层图案和控制栅电极之间。还讨论了相关方法。

9. 发明申请

US20120068245A1 NON-VOLATILE MEMORY DEVICES INCLUDING BLOCKING INSULATION PATTERNS WITH SUB-LAYERS HAVING DIFFERENT ENERGY BAND GAPS 有权
标题翻译：非易失性存储器件，包括具有不同能量带GAAS的子层的阻塞绝缘图案
公开(公告)号：US20120068245A1
公开(公告)日：2012-03-22
申请号：US13305930
申请日：2011-11-29
申请人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
发明人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11517 , H01L27/11529 , H01L27/11563 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/42348 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7883
摘要： A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底和半导体衬底上的隔离层，其中隔离层限定半导体衬底的有源区。可以在半导体衬底的有源区上设置隧道绝缘层，并且可以在隧道绝缘层上设置电荷存储图案。可以在电荷存储图案上提供界面层图案，并且可以在界面层图案上提供阻挡绝缘图案。此外，块绝缘图案可以包括高k介电材料，并且界面层图案和阻挡绝缘图案可以包括不同的材料。可以在阻挡绝缘层上设置控制栅电极，使得阻挡绝缘图案位于界面层图案和控制栅电极之间。还讨论了相关方法。

10. 发明授权

US07776687B2 Semiconductor device having a gate contact structure capable of reducing interfacial resistance and method of forming the same 有权
标题翻译：具有能够降低界面电阻的栅极接触结构的半导体器件及其形成方法
公开(公告)号：US07776687B2
公开(公告)日：2010-08-17
申请号：US11797401
申请日：2007-05-03
申请人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
发明人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/823462 , H01L21/823475 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.
摘要翻译：半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的接触插塞使多晶硅层通过开口接触。

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