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1. 发明授权

US08748286B2 Method of fabricating a nonvolatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US08748286B2
公开(公告)日：2014-06-10
申请号：US13198157
申请日：2011-08-04
申请人： Jong-Hoon Na , Young-Woo Park , Dong-Hwa Kwak , Tae-Yong Kim , Jee-Hoon Han , Jang-Hyun You , Dong-Sik Lee , Su-Jin Park
发明人： Jong-Hoon Na , Young-Woo Park , Dong-Hwa Kwak , Tae-Yong Kim , Jee-Hoon Han , Jang-Hyun You , Dong-Sik Lee , Su-Jin Park
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L27/0207 , H01L21/28273 , H01L27/11 , H01L27/11519 , H01L27/11524
摘要： A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.
摘要翻译：一种制造非易失性存储器件的方法包括提供具有由多个沟槽限定的有源区的衬底，在具有多个沟槽的衬底上形成第一隔离层，在第一隔离层上形成牺牲层以填充沟槽，所述牺牲层包括填充所述沟槽的下部的第一区域和除所述下部以外的第二区域填充部分，去除所述牺牲层的所述第二区域，在所述第一隔离层上形成第二隔离层和在所述第一隔离层的所述第一区域牺牲层，通过去除牺牲层的第一区域在沟槽中形成气隙，以及在保持气隙的同时去除第一隔离层的一部分和第二隔离层的一部分。

2. 发明申请

US20120122297A1 METHOD OF FABRICATING A NONVOLATILE MEMORY DEVICE 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20120122297A1
公开(公告)日：2012-05-17
申请号：US13198157
申请日：2011-08-04
申请人： Jong-Hoon NA , Young-Woo Park , Dong-Hwa Kwak , Tae-Yong Kim , Jee-Hoon Han , Jang-Hyun You , Dong-Sik Lee , Su-Jin Park
发明人： Jong-Hoon NA , Young-Woo Park , Dong-Hwa Kwak , Tae-Yong Kim , Jee-Hoon Han , Jang-Hyun You , Dong-Sik Lee , Su-Jin Park
IPC分类号： H01L21/762
CPC分类号： H01L27/0207 , H01L21/28273 , H01L27/11 , H01L27/11519 , H01L27/11524
摘要： A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.
摘要翻译：一种制造非易失性存储器件的方法包括提供具有由多个沟槽限定的有源区的衬底，在具有多个沟槽的衬底上形成第一隔离层，在第一隔离层上形成牺牲层以填充沟槽，所述牺牲层包括填充所述沟槽的下部的第一区域和除所述下部以外的第二区域填充部分，去除所述牺牲层的所述第二区域，在所述第一隔离层上形成第二隔离层和在所述第一隔离层的所述第一区域牺牲层，通过去除牺牲层的第一区域在沟槽中形成气隙，以及在保持气隙的同时去除第一隔离层的一部分和第二隔离层的一部分。

3. 发明授权

US07525173B2 Layout structure of MOS transistors on an active region 失效
标题翻译：有源区MOS晶体管的布局结构
公开(公告)号：US07525173B2
公开(公告)日：2009-04-28
申请号：US11485341
申请日：2006-07-13
申请人： Hyang-Ja Yang , Su-Jin Park , Uk-Rae Cho , Sung-Hoon Kim
发明人： Hyang-Ja Yang , Su-Jin Park , Uk-Rae Cho , Sung-Hoon Kim
IPC分类号： H01L29/78
CPC分类号： H01L27/0203 , H01L21/823418 , H01L21/823481
摘要： In a layout structure of a plurality of metal oxide semiconductor (MOS) transistors, the layout structure may include a first group of MOS transistors having first drain regions and first source regions that are individually allocated to a group active region that is isolated from all sides by a trench isolation, and a second group of MOS transistors having second drain regions and second source regions allocated to the group active region. The second group is disposed between the first group and an edge of the group active region. One or both of the first drain regions and first source regions are not in contact with an edge of the trench isolation in a length direction of a finger-type gate electrode.
摘要翻译：在多个金属氧化物半导体（MOS）晶体管的布局结构中，布局结构可以包括具有第一漏极区域的第一组MOS晶体管和分别分配给与所有侧面隔离的组有源区域的第一源极区域通过沟槽隔离，以及第二组MOS晶体管，其具有分配给组有源区的第二漏极区和第二源极区。第二组布置在第一组与组有源区的边缘之间。第一漏极区域和第一源极区域中的一个或两个不与指状栅电极的长度方向上的沟槽隔离边缘接触。

4. 发明授权

US09286823B2 Method and apparatus for reducing power consumption in electronic equipment using self-emitting type display 有权
标题翻译：使用自发式显示器降低电子设备功耗的方法和装置
公开(公告)号：US09286823B2
公开(公告)日：2016-03-15
申请号：US12720902
申请日：2010-03-10
申请人： Su-Jin Park , Hark-Sang Kim , Sang-Ryul Park
发明人： Su-Jin Park , Hark-Sang Kim , Sang-Ryul Park
IPC分类号： G09G5/10 , G09G3/22 , G09G3/32
CPC分类号： G09G3/22 , G09G3/3208 , G09G2320/0271 , G09G2320/0613 , G09G2320/0626 , G09G2320/106 , G09G2330/021 , G09G2340/10 , G09G2340/12
摘要： A method for reducing power consumption in an electronic equipment using a self-emitting type display is provided. The method includes distinguishing image data to be output, correcting each distinguished image data into an image brightness, synthesizing the corrected image data into one piece of output image data, and controlling a driving power for displaying the synthesized output image data as an image.
摘要翻译：提供了一种使用自发式显示器来降低电子设备的功耗的方法。该方法包括区分要输出的图像数据，将每个识别的图像数据校正为图像亮度，将校正的图像数据合成为一条输出图像数据，以及控制用于显示合成输出图像数据的驱动力作为图像。

5. 发明申请

US20060224814A1 Semiconductor memory devices having controllable input/output bit architectures and related methods 有权
标题翻译：具有可控输入/输出位结构和相关方法的半导体存储器件
公开(公告)号：US20060224814A1
公开(公告)日：2006-10-05
申请号：US11358798
申请日：2006-02-21
申请人： Sung-Hoon Kim , Seong-Jin Jang , Su-Jin Park
发明人： Sung-Hoon Kim , Seong-Jin Jang , Su-Jin Park
IPC分类号： G06F12/06
CPC分类号： G11C7/22
摘要： A semiconductor memory device may include a semiconductor substrate, a first unit memory device on the substrate, and a second unit memory device on the substrate. The first unit memory device may be configured to receive first through Nth data bits and/or to provide first through Nth data bits to an external device in response to a command signal, an address signal, and a clock signal, and in response to a first chip selection signal. The second unit memory device may be configured to receive (N+1)th through 2Nth data bits and/or to provide (N+1)th through 2Nth data bits to an external device in response to the command signal, the address signal, and the clock signal, and in response to a second chip selection signal. Related methods are also discussed.
摘要翻译：半导体存储器件可以包括半导体衬底，衬底上的第一单元存储器件和衬底上的第二单元存储器件。第一单元存储器件可以被配置为响应于命令接收第一至第N个/或以上数据位和/或向外部设备提供第一至第N个/ 信号，地址信号和时钟信号，以及响应于第一芯片选择信号。第二单元存储器件可以被配置为通过2N个第（N）个数据位接收（N + 1）个第个和/或提供（N + 1）响应于命令信号，地址信号和时钟信号，以及响应于第二芯片选择信号，向外部设备提供/ SUP>至2N第数据位。还讨论了相关方法。

6. 发明申请

US20140248382A1 CURCUMINOID-BASED COMPOUND/STEVIOSIDE-CONTAINING COMPLEX FOR THE PREVENTION AND TREATMENT OF AN INFLUENZA VIRUS INFECTION 审中-公开
标题翻译：用于预防和治疗流感病毒感染的基于基于CURCUMINIID的化合物/含有维生素E的复合物
公开(公告)号：US20140248382A1
公开(公告)日：2014-09-04
申请号：US14126106
申请日：2012-06-13
申请人： Woo-Song Lee , Young-Bae Ryu , Young-Min Kim , Su-Jin Park , Mun-Chual Rho , Hyung-Jae Jeong , Hyung-Jun Kwon
发明人： Woo-Song Lee , Young-Bae Ryu , Young-Min Kim , Su-Jin Park , Mun-Chual Rho , Hyung-Jae Jeong , Hyung-Jun Kwon
IPC分类号： A61K31/704 , A23L1/30 , A61K36/28 , A61K31/12 , A61K36/9066
CPC分类号： A61K31/704 , A23K20/111 , A23K20/163 , A23K50/10 , A23K50/30 , A23K50/75 , A23L33/105 , A61K31/12 , A61K36/28 , A61K36/9066 , A61K47/6921 , A61K2300/00
摘要： The present invention relates to a complex comprising a compound of formula (I), or a plant extract comprising the compound or a fraction thereof; and stevioside, or a plant extract comprising the stevioside or a fraction thereof, and relates to a pharmaceutical composition for preventing or treating an influenza virus infection comprising the complex as an active ingredient. Also, the present invention relates to a food composition for preventing or improving an influenza virus infection, a virucidal quasi-drug composition, a virucidal feed additive, and a feed, which comprises the complex as an active ingredient. According to the present invention, the complex comprising a compound of formula (I), or a plant extract comprising the compound or a fraction thereof; and stevioside, or a plant extract comprising the stevioside or a fraction thereof exhibits a virucidal effect and an effect of inhibiting cell degradation against an influenza virus as well as antiviral efficacy in a specific pathogen-free (SPF) chicken, and thus can be usefully used in the prevention and treatment of an influenza virus infection.
摘要翻译：本发明涉及包含式（I）化合物或包含该化合物或其部分的植物提取物的复合物; 还包括甜菊糖苷或其一部分的植物提取物，涉及用于预防或治疗包含该复合物作为活性成分的流感病毒感染的药物组合物。此外，本发明涉及用于预防或改善流感病毒感染的食品组合物，杀病毒准药物组合物，杀病毒饲料添加剂和饲料，其包含该复合物作为活性成分。根据本发明，包含式（I）化合物或包含该化合物或其部分的植物提取物的复合物; 甜菊糖苷或甜菊糖苷或其部分的植物提取物表现出对特定无病原体（SPF）鸡中的抗病毒效果和抑制细胞降解对流感病毒的抗病毒效果的效果，因此可以有用地用于预防和治疗流感病毒感染。

7. 发明授权

US08130028B2 CMOS charge pump with improved latch-up immunity 有权
标题翻译： CMOS电荷泵具有提高的闭锁抑制能力
公开(公告)号：US08130028B2
公开(公告)日：2012-03-06
申请号：US12691937
申请日：2010-01-22
申请人： Su-Jin Park , Joung-Yeal Kim , Bai-Sun Kong , Young-Hyun Jun
发明人： Su-Jin Park , Joung-Yeal Kim , Bai-Sun Kong , Young-Hyun Jun
IPC分类号： G05F3/02
CPC分类号： H02M3/07
摘要： A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.
摘要翻译：提供了具有提高的闭锁电阻的CMOS电荷泵。 CMOS电荷泵包括阻塞晶体管，其响应于阻塞控制信号将第一和第二升压节点与体节点断开，使得体电压可以保持在预定水平或更高水平。在上电期间的CMOS电荷泵首先在主泵进行升压操作之前预充电体积电压并且防止闩锁现象。

8. 发明申请

US20100069625A1 PROCESS FOR PREPARING OF 2'-DEOXY-2'2'-DIFLUOROCYTIDINE 失效
标题翻译：制备2'-脱氧-2'-脱氧胆碱的方法
公开(公告)号：US20100069625A1
公开(公告)日：2010-03-18
申请号：US12532331
申请日：2008-03-20
申请人： Su-Jin Park , Chun-Rim Oh , Young-Deuck Kim
发明人： Su-Jin Park , Chun-Rim Oh , Young-Deuck Kim
IPC分类号： C07H19/06 , C07H3/02 , C07D317/08
CPC分类号： C07H1/00 , C07H19/06 , Y02P20/55
摘要： Disclosed is a method for preparing 2′-deoxy-2′,2′-difluorocytidine of Formula I comprising, preparing an optically pure 3R-hydroxypropane amide compound of Formula VIII from an optical ester compound of Formula IX using an optically active chiral amine, preparing an optically pure D-erythro-2,2-difluoro-2-deoxy-1-oxoribose compound of Formula V from the compound of Formula VIII, glycosylating the compound of Formula V with a nucleobase to prepare the 2′-deoxy-2′,2′-difluorocytidine of Formula I as a β-nucleoside. With the present invention, it is possible to prepare an optically pure compound of Formula I in a high purity and a high yield. In the Formulae, R1 and R2 are protecting groups and are each independently benzoyl, 4-methylbenzoyl, 3-methylbenzoyl, 4-cyanobenzoyl, 3-cyanobenzoyl, 4-propylbenzoyl, 2-ethoxybenzoyl, 4-t-butylbenzoyl, 1-naphthoyl or 2-naphthoyl, R3, R4 and R7 are each independently C1-C3 alkyl, R5 is methyl or ethyl, R6 is hydrogen, methyl or methoxy.
摘要翻译：公开了一种制备式I的2'-脱氧-2'，2'-二氟胞苷的方法，其包括：使用光学活性手性胺由式IX的光学酯化合物制备光学纯的3R-羟基丙酰胺化合物，从式VIII化合物制备光学纯的D-型赤式-2,2-二氟-2-脱氧-1-氧代核糖核糖化合物，用式I化合物将式V化合物糖基化，从而制备2'-脱氧-2 '，式Ⅰ的2'-二氟胞苷作为核苷。通过本发明，可以以高纯度和高收率制备光学纯的式I化合物。在式中，R 1和R 2是保护基，各自独立地是苯甲酰基，4-甲基苯甲酰基，3-甲基苯甲酰基，4-氰基苯甲酰基，3-氰基苯甲酰基，4-丙基苯甲酰基，2-乙氧基苯甲酰基，4-叔丁基苯甲酰基，1-萘甲酰基或 2-萘甲酰基，R3，R4和R7各自独立地为C1-C3烷基，R5为甲基或乙基，R6为氢，甲基或甲氧基。

9. 发明授权

US07479936B2 Plasma display and its driving method and circuit 失效
标题翻译：等离子显示及其驱动方法和电路
公开(公告)号：US07479936B2
公开(公告)日：2009-01-20
申请号：US11511271
申请日：2006-08-29
申请人： Su-Jin Park
发明人： Su-Jin Park
IPC分类号： G09G3/28
CPC分类号： G09G3/2965 , G09G3/294
摘要： A plasma display has a first power recovery unit including a first inductor having a first end coupled to a second electrode and a second power recovery unit including a second inductor having a first end coupled to the second electrode, the second inductor having an inductance different from that of the first inductor and alternately supplying a second voltage that is greater than a first voltage and a third voltage that is less than the first voltage to the second electrode, while the first voltage is supplied to the first electrode, during a sustain period. A first path between the first inductor and second electrode has a different length from that of a second path between the second inductor and the second electrode, and an inductor on a longer path among the first and second paths has a smaller inductance than that of an inductor on a shorter path among the first and second paths. When the inductance of the inductor on the longer path of the two power recovery circuit paths is set to be relatively smaller, the impedance can be compensated for by the parasitic inductances on the longer path.
摘要翻译：等离子体显示器具有第一功率回收单元，其包括具有耦合到第二电极的第一端的第一电感器和包括具有耦合到第二电极的第一端的第二电感器的第二功率回收单元，所述第二电感器具有不同于在维持期间，向第一电极提供第一电压，并将第一电压提供给第一电极，并且向第二电极提供大于第一电压的第二电压和小于第一电压的第三电压。第一电感器和第二电极之间的第一路径具有与第二电感器和第二电极之间的第二路径的长度不同的长度，并且在第一和第二路径中较长路径上的电感器具有比电感器在第一和第二路径中的较短路径上。当两个功率恢复电路路径的较长路径上的电感器的电感被设置为相对较小时，可以通过较长路径上的寄生电感补偿阻抗。

10. 发明申请

US20070085768A1 Plasma display and its driving method and circuit 失效
标题翻译：等离子显示及其驱动方法和电路
公开(公告)号：US20070085768A1
公开(公告)日：2007-04-19
申请号：US11511271
申请日：2006-08-29
申请人： Su-Jin Park
发明人： Su-Jin Park
IPC分类号： G09G3/28
CPC分类号： G09G3/2965 , G09G3/294
摘要： A plasma display has a first power recovery unit including a first inductor having a first end coupled to a second electrode and a second power recovery unit including a second inductor having a first end coupled to the second electrode, the second inductor having an inductance different from that of the first inductor and alternately supplying a second voltage that is greater than a first voltage and a third voltage that is less than the first voltage to the second electrode, while the first voltage is supplied to the first electrode, during a sustain period. A first path between the first inductor and second electrode has a different length from that of a second path between the second inductor and the second electrode, and an inductor on a longer path among the first and second paths has a smaller inductance than that of an inductor on a shorter path among the first and second paths. When the inductance of the inductor on the longer path of the two power recovery circuit paths is set to be relatively smaller, the impedance can be compensated for by the parasitic inductances on the longer path.
摘要翻译：等离子体显示器具有第一功率回收单元，其包括具有耦合到第二电极的第一端的第一电感器和包括具有耦合到第二电极的第一端的第二电感器的第二功率回收单元，所述第二电感器具有不同于在维持期间，向第一电极提供第一电压，并将第一电压提供给第一电极，并且向第二电极提供大于第一电压的第二电压和小于第一电压的第三电压。第一电感器和第二电极之间的第一路径具有与第二电感器和第二电极之间的第二路径的长度不同的长度，并且在第一和第二路径中较长路径上的电感器具有比电感器在第一和第二路径中的较短路径上。当两个功率恢复电路路径的较长路径上的电感器的电感被设置为相对较小时，可以通过较长路径上的寄生电感补偿阻抗。

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