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1. 发明申请

US20110084329A1 NON-VOLATILE MEMORY DEVICE 失效
标题翻译：非易失性存储器件
公开(公告)号：US20110084329A1
公开(公告)日：2011-04-14
申请号：US12713736
申请日：2010-02-26
申请人： Jang-hyun YOU , Jin-taek Park , Young-woo Park , Jung-dal Choi
发明人： Jang-hyun YOU , Jin-taek Park , Young-woo Park , Jung-dal Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11565 , H01L27/11573 , H01L29/4234
摘要： A non-volatile memory device includes a semiconductor layer including a cell region and a peripheral region, a cell region gate structure disposed in the cell region of the semiconductor layer, and wherein the cell region gate structure includes a tunneling insulating layer and a first blocking insulating layer, a second blocking insulating layer, and a third blocking insulating layer. The non-volatile memory device further includes a peripheral region gate structure formed in the peripheral region of the semiconductor layer. The peripheral region gate structure includes a first peripheral region insulating layer including a same material as a material included in the tunneling insulating layer and a second peripheral region insulating layer including a same material as a material included in the third blocking insulating layer.
摘要翻译：非易失性存储器件包括包括单元区域和外围区域的半导体层，设置在半导体层的单元区域中的单元区域栅极结构，并且其中单元区域栅极结构包括隧道绝缘层和第一阻挡层绝缘层，第二阻挡绝缘层和第三阻挡绝缘层。非易失性存储器件还包括形成在半导体层的周边区域中的外围区域栅极结构。周边区域栅极结构包括：第一周边区域绝缘层，其包括与包含在隧道绝缘层中的材料相同的材料;以及第二周边区域绝缘层，其包括与包含在第三阻挡绝缘层中的材料相同的材料。

2. 发明授权

US08169018B2 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US08169018B2
公开(公告)日：2012-05-01
申请号：US12713736
申请日：2010-02-26
申请人： Jang-hyun You , Jin-taek Park , Young-woo Park , Jung-dal Choi
发明人： Jang-hyun You , Jin-taek Park , Young-woo Park , Jung-dal Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11565 , H01L27/11573 , H01L29/4234
摘要： A non-volatile memory device includes a semiconductor layer including a cell region and a peripheral region, a cell region gate structure disposed in the cell region of the semiconductor layer, and wherein the cell region gate structure includes a tunneling insulating layer and a first blocking insulating layer, a second blocking insulating layer, and a third blocking insulating layer. The no-volatile memory device further includes a peripheral region gate structure formed in the peripheral region of the semiconductor layer. The peripheral region gate structure includes a first peripheral region insulating layer including a same material as a material included in the tunneling insulating layer and a second peripheral region insulating layer including a same material as a material included in the third blocking insulating layer.
摘要翻译：非易失性存储器件包括包括单元区域和外围区域的半导体层，设置在半导体层的单元区域中的单元区域栅极结构，并且其中单元区域栅极结构包括隧道绝缘层和第一阻挡层绝缘层，第二阻挡绝缘层和第三阻挡绝缘层。非易失性存储器件还包括形成在半导体层的周边区域中的外围区域栅极结构。周边区域栅极结构包括：第一周边区域绝缘层，其包括与包含在隧道绝缘层中的材料相同的材料;以及第二周边区域绝缘层，其包括与包含在第三阻挡绝缘层中的材料相同的材料。

3. 发明申请

US20060022276A1 Methods of forming semiconductor devices including a resistor in a resistor region and devices so formed 审中-公开
标题翻译：在电阻器区域中形成包括电阻器的半导体器件的形成方法和如此形成的器件
公开(公告)号：US20060022276A1
公开(公告)日：2006-02-02
申请号：US11023892
申请日：2004-12-28
申请人： Jin-taek Park , Jung-dal Choi , Sung-hoi Hur , Joon-hee Lee
发明人： Jin-taek Park , Jung-dal Choi , Sung-hoi Hur , Joon-hee Lee
IPC分类号： H01L29/94
CPC分类号： H01L27/11526 , H01L27/0629 , H01L27/105 , H01L27/115 , H01L27/11529 , H01L27/11531 , H01L28/20
摘要： Methods of forming a semiconductor device can include forming a first conductive layer of a gate electrode on a substrate of a device and forming a second conductive layer of a resistor, that is different than the first conductive layer, on the substrate spaced-apart from the gate electrode. Related devices are also disclosed.
摘要翻译：形成半导体器件的方法可以包括在器件的衬底上形成栅电极的第一导电层，并且在与第一导电层隔开的衬底上形成与第一导电层不同的电阻器的第二导电层栅电极。还公开了相关设备。

4. 发明申请

US20150008499A1 VERTICAL SEMICONDUCTOR DEVICE 有权
标题翻译：垂直半导体器件
公开(公告)号：US20150008499A1
公开(公告)日：2015-01-08
申请号：US14267909
申请日：2014-05-02
申请人： Jae-goo Lee , Young-woo Park , Jin-taek Park
发明人： Jae-goo Lee , Young-woo Park , Jin-taek Park
IPC分类号： H01L29/78 , H01L29/792 , H01L29/788
CPC分类号： H01L27/11582 , H01L23/5226 , H01L27/11273 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/785 , H01L29/7889 , H01L29/7926
摘要： A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.
摘要翻译：垂直半导体器件包括从垂直于衬底的上表面的第一方向上从衬底延伸的沟道结构，以及顺序地形成在沟道结构的侧表面上的接地选择线，字线和串选择线第一个要相互分离的方向。通道结构包括形成在通道结构的侧壁部分之间的突出区域，其在接地选择线和衬底的上表面之间，突出区域在与第一方向垂直的水平方向上突出。

5. 发明授权

US10263009B2 Semiconductor devices with vertical channel structures 有权
公开(公告)号：US10263009B2
公开(公告)日：2019-04-16
申请号：US15722216
申请日：2017-10-02
申请人： Chang-hyun Lee , Jin-taek Park , Young-woo Park
发明人： Chang-hyun Lee , Jin-taek Park , Young-woo Park
IPC分类号： H01L29/792 , H01L27/11582 , H01L29/78 , H01L29/10 , H01L27/1157 , H01L27/11556 , H01L27/11524
摘要： Semiconductor devices are provided. The semiconductor devices may include a substrate, a ground selection gate electrode, and a channel structure. The channel structure may extend the ground selection gate electrode in a first direction perpendicular to a top surface of the substrate, and include a channel layer, a channel contact layer, and a stepped portion. The channel contact layer may contact the substrate and include a first width in a second direction perpendicular to the first direction. The channel layer may contact the channel contact layer, include a bottom surface between a bottom surface of the ground selection gate electrode and the top surface of the substrate in the first direction, and include a second width in the second direction different from the first width.

6. 发明授权

US08653585B2 Nonvolatile memory device including a channel pad having a channel extending portion and a spacer and method of manufacturing the same 有权
标题翻译：包括具有通道延伸部分的通道焊盘和间隔件的非易失性存储器件及其制造方法
公开(公告)号：US08653585B2
公开(公告)日：2014-02-18
申请号：US13404047
申请日：2012-02-24
申请人： Eun-sun Youm , Sang-yong Park , Jin-taek Park , Yong-top Kim
发明人： Eun-sun Youm , Sang-yong Park , Jin-taek Park , Yong-top Kim
IPC分类号： H01L29/66
CPC分类号： H01L27/11556 , H01L27/11582 , H01L29/7926
摘要： A nonvolatile memory device having a vertical structure and a method of manufacturing the same, the nonvolatile memory device including a channel region that vertically extends from a substrate; gate electrodes on the substrate, the gate electrodes being disposed along an outer side wall of the channel region and spaced apart from one another; and a channel pad that extends from one side of the channel region to an outside of the channel region, the channel pad covering a top surface of the channel region.
摘要翻译：一种具有垂直结构的非易失性存储器件及其制造方法，所述非易失性存储器件包括从衬底垂直延伸的沟道区域; 所述栅极电极沿着所述沟道区域的外侧壁设置并且彼此间隔开; 以及沟道垫，其从所述沟道区的一侧延伸到所述沟道区的外部，所述沟道衬垫覆盖所述沟道区的顶表面。

7. 发明申请

US20120238093A1 Methods of Fabricating Semiconductor Devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120238093A1
公开(公告)日：2012-09-20
申请号：US13418585
申请日：2012-03-13
申请人： Sang-yong Park , Woon-kyung Lee , Jin-taek Park
发明人： Sang-yong Park , Woon-kyung Lee , Jin-taek Park
IPC分类号： H01L21/768
CPC分类号： H01L21/76802 , H01L21/311 , H01L21/76838 , H01L21/76877 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n−1 first recesses penetrating 20 through 2n−1 deposited sacrificial layers and forming a buried insulating layer group including 2n−1 buried insulating layers filling the 2n−1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n−1 buried insulating layers may be formed.
摘要翻译：一种制造半导体器件的方法包括形成层叠结构，其中分别沉积有牺牲层的2n（n为2以上的整数）和设置在2n个沉积的牺牲层上的2n个沉积的绝缘层交替地沉积在第三垂直于第一方向和第二方向的方向在具有在彼此垂直的第一和第二方向上延伸的上表面的基板上。方法包括形成包括通过2n-1个沉积的牺牲层穿透20的2n-1个第一凹部的凹陷组，并且分别形成包括2n-1个第一凹部的2n-1个掩埋绝缘层的掩埋绝缘层组。可以形成包括穿过2n个沉积绝缘层的最上层的绝缘层和2n-1个绝缘层的2n个接触插塞的接触插塞组。

8. 发明授权

US08906805B2 Methods of fabricating semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08906805B2
公开(公告)日：2014-12-09
申请号：US13418585
申请日：2012-03-13
申请人： Sang-yong Park , Woon-kyung Lee , Jin-taek Park
发明人： Sang-yong Park , Woon-kyung Lee , Jin-taek Park
IPC分类号： H01L21/768 , H01L29/788 , H01L29/792 , H01L27/115
CPC分类号： H01L21/76802 , H01L21/311 , H01L21/76838 , H01L21/76877 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n−1 first recesses penetrating 20 through 2n−1 deposited sacrificial layers and forming a buried insulating layer group including 2n−1 buried insulating layers filling the 2n−1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n−1 buried insulating layers may be formed.
摘要翻译：一种制造半导体器件的方法包括形成层叠结构，其中分别沉积有牺牲层的2n（n为2以上的整数）和设置在2n个沉积的牺牲层上的2n个沉积的绝缘层交替地沉积在第三垂直于第一方向和第二方向的方向在具有在彼此垂直的第一和第二方向上延伸的上表面的基板上。方法包括形成包括通过2n-1个沉积的牺牲层穿透20的2n-1个第一凹部的凹陷组，并且分别形成包括2n-1个第一凹部的2n-1个掩埋绝缘层的掩埋绝缘层组。可以形成包括穿过2n个沉积绝缘层的最上层的绝缘层和2n-1个绝缘层的2n个接触插塞的接触插塞组。

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