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1. 发明授权

US09632777B2 Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry 有权
公开(公告)号：US09632777B2
公开(公告)日：2017-04-25
申请号：US13566141
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Embodiments relate to packed loading and storing of data. An aspect includes a method for packed loading and storing of data distributed in a system that includes memory and a processing element. The method includes fetching and decoding an instruction for execution by the processing element. The processing element gathers a plurality of individually addressable data elements from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The data elements are packed and loaded into register file elements of a register file entry by the processing element based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.

2. 发明申请

US20080147982A1 CACHE LINE REPLACEMENT TECHNIQUES ALLOWING CHOICE OF LFU OR MFU CACHE LINE REPLACEMENT 有权
标题翻译：采用LFU或MFU高速缓存行替代方式的高速缓存行替换技术
公开(公告)号：US20080147982A1
公开(公告)日：2008-06-19
申请号：US11523485
申请日：2006-09-19
申请人： Richard Edward Matick , Jaime H. Moreno , Malcolm Scott Ware
发明人： Richard Edward Matick , Jaime H. Moreno , Malcolm Scott Ware
IPC分类号： G06F12/00
CPC分类号： H04W12/06 , G06F12/122 , G06F12/127 , H04L63/0853 , Y02D10/13
摘要： Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed. The cache additionally comprises MFU circuitry (1) adapted to produce new state information for the at least two given cache lines in response to an access to one of the at least two given cache lines, and (2) when a cache miss occurs in one of the at least two given cache lines, adapted to determine, based on the new state information, which of the at least two given cache lines is the most frequently used cache line.
摘要翻译：公开了允许选择最低频（LFU）或最常用（MFU）高速缓存线替换的方法和装置。所述方法和装置确定高速缓存中多个高速缓存行的至少两个给定高速缓存行的新状态信息，所述新状态信息至少部分地基于所述至少两个给定高速缓存行的先前状态信息。另外，当在至少两条给定行之一中存在访问错误时，方法和装置（1）选择LFU或MFU替换标准，以及（2）基于新的状态信息和所选择的替换标准。另外，公开了用于替换MFU高速缓存线的高速缓存。高速缓存还包括MFU电路（1），其适于响应于对至少两个给定高速缓存行中的一个的访问而产生用于所述至少两个给定高速缓存行的新状态信息，以及（2）当高速缓存未命中出现在一个所述至少两个给定高速缓存行适于基于所述新状态信息确定所述至少两个给定高速缓存行中的哪一个是最常用的高速缓存行。

3. 发明授权

US06948051B2 Method and apparatus for reducing logic activity in a microprocessor using reduced bit width slices that are enabled or disabled depending on operation width 失效
标题翻译：使用减少的位宽度切片减少微处理器中的逻辑活动的方法和装置，其根据操作宽度被启用或禁用
公开(公告)号：US06948051B2
公开(公告)日：2005-09-20
申请号：US09855241
申请日：2001-05-15
申请人： Jude A. Rivers , Jaime H. Moreno , Vinodh R. Cuppu
发明人： Jude A. Rivers , Jaime H. Moreno , Vinodh R. Cuppu
IPC分类号： G06F9/30 , G06F9/302 , G06F9/38 , G06F9/318
CPC分类号： G06F9/3891 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/3016 , G06F9/30192 , G06F9/3887
摘要： A method and apparatus for reducing logic activity in a microprocessor which examines every instruction before it is executed and determines in advance the minimum appropriate datapath width (in byte or half-word quantities) necessary to accurately execute the operation. Achieving this requires two major enhancements to a traditional microprocessor pipeline. First, extra logic (potentially an extra pipeline stage for determining an operation's effective bit width—the WD width detection logic) is introduced between the Decode and Execution stages. Second, the traditional Execution stage architecture (including a register file RF and the arithmetic logical unit ALU), instead of being organized as one continuous 32-bit unit, is organized as a collection of multiple slices, where a slice can be of an 8-bit (a byte) or a 16-bit (double byte) granularity. Each slice in this case can operate independently of each other slice, and includes portion of the register file, functional unit and cache memory. Concatenating a multiple number of these slices together creates a required full width processor.
摘要翻译：一种用于减少微处理器中的逻辑活动的方法和装置，其在执行之前检查每个指令，并且预先确定准确执行该操作所需的最小适当的数据路径宽度（以字节或半字数量）。实现这一点需要对传统微处理器管道进行两个主要的改进。首先，在解码和执行阶段之间引入额外的逻辑（潜在的用于确定操作的有效位宽度的额外流水线级 - WD宽度检测逻辑）。第二，传统的执行阶段架构（包括寄存器文件RF和算术逻辑单元ALU）而不是组织为一个连续的32位单元，被组织为多个片段的集合，其中片可以是8 位（一个字节）或一个16位（双字节）粒度。在这种情况下，每个切片可独立于每个切片进行操作，并且包括寄存器文件，功能单元和高速缓冲存储器的部分。将多个这些切片连接在一起创建所需的全宽处理器。

4. 发明授权

US06711651B1 Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetching 有权
标题翻译：用于使用推取预取的多处理器系统的相干高速缓冲存储器中共享数据的基于历史的移动的方法和装置
公开(公告)号：US06711651B1
公开(公告)日：2004-03-23
申请号：US09655642
申请日：2000-09-05
申请人： Jaime H. Moreno , Jude A. Rivers , John-David Wellman
发明人： Jaime H. Moreno , Jude A. Rivers , John-David Wellman
IPC分类号： G06F1300
CPC分类号： G06F12/0862 , G06F12/0815 , G06F2212/6024
摘要： A method and apparatus are provided for moving at least one of instructions and operand data throughout a plurality of caches included in a multiprocessor computer system, wherein each of the plurality of caches is included in one of a plurality of processing nodes of the system so as to provide history-based movement of shared-data in coherent cache memories. A plurality of entries are stored in a consume after produce (CAP) table attached to each of the plurality of caches. Each of the entries is associated with a plurality of storage elements in one of the plurality of caches and includes information of prior usage of the plurality of storage elements by each of the plurality of processing nodes. Upon a miss by a processing node to a cache included therein, any storage elements that caused the miss are transferred to the cache from one of main memory and another cache. An entry is created in the table that is associated with the storage elements that caused the miss. A push prefetching engine may be used to create the entry.
摘要翻译：提供了一种方法和装置，用于在包括在多处理器计算机系统中的多个高速缓存中移动指令和操作数数据中的至少一个，其中多个高速缓存中的每一个包括在系统的多个处理节点之一中，以便以共享缓存存储器中的共享数据提供基于历史的移动。在附加到多个高速缓存中的每一个的产生（CAP）表之后，将多个条目存储在消费中。每个条目与多个高速缓存之一中的多个存储元件相关联，并且包括多个处理节点中的每一个的多个存储元件的先前使用的信息。当处理节点错过其中包含的高速缓存时，导致未命中的任何存储元件从主存储器和另一高速缓存之一传送到高速缓存。在表中创建一个与导致未命中的存储元素相关联的条目。推式预取引擎可用于创建条目。

5. 发明授权

US06704855B1 Method and apparatus for reducing encoding needs and ports to shared resources in a processor 失效
标题翻译：用于将编码需求和端口减少到处理器中的共享资源的方法和装置
公开(公告)号：US06704855B1
公开(公告)日：2004-03-09
申请号：US09585766
申请日：2000-06-02
申请人： Erik R. Altman , Jaime H. Moreno , Mayan Moudgill
发明人： Erik R. Altman , Jaime H. Moreno , Mayan Moudgill
IPC分类号： G06F930
CPC分类号： G06F9/30098 , G06F9/30141 , G06F9/3016 , G06F9/3824 , G06F9/3853
摘要： The present invention relates to a method for accessing elements from a shared resource to be used by consumers that perform actions according to corresponding operations. The method creates a packet of operations to be processed simultaneously, wherein the elements from the shared resource used by the operations are specified by source and destination identifier fields that are shared among the operations in such a way that the sum of all the elements from the shared resource used by the operations does not exceed a total number of identifiers available in the packet. The method also reads the elements from the shared resource according to the shared identifier fields specified in the packet. The method decodes a number of elements from the shared resource needed by each operation, by passing the operations to an operation decoder having a defined routing scheme based on the needs of the operations. The method also routes the elements to the consumers performing operations and resulting values to the shared resource, according to a routing signal of the operation decoder.
摘要翻译：本发明涉及一种从共享资源访问要由使用者根据相应操作执行动作的消费者的方法。该方法创建要同时处理的一组操作，其中由操作使用的来自共享资源的元素由在操作之间共享的源和目标标识符字段指定，使得来自操作使用的共享资源不会超过数据包中可用的标识符的总数。该方法还根据分组中指定的共享标识符字段从共享资源中读取元素。该方法根据操作的需要，通过将操作传递给具有定义的路由方案的操作解码器，从每个操作所需的共享资源中解码多个元素。该方法还根据操作解码器的路由信号将元素路由到消费者对共享资源执行操作和结果值。

6. 发明授权

US5625835A Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor 失效
标题翻译：用于在超标量或非常长的指令字处理器中重新排序存储器操作的方法和装置
公开(公告)号：US5625835A
公开(公告)日：1997-04-29
申请号：US435411
申请日：1995-05-10
申请人： Mahmut K. Ebcioglu , David A. Luick , Jaime H. Moreno , Gabriel M. Silberman , Philip B. Winterfield
发明人： Mahmut K. Ebcioglu , David A. Luick , Jaime H. Moreno , Gabriel M. Silberman , Philip B. Winterfield
IPC分类号： G06F9/38
CPC分类号： G06F9/383 , G06F9/30043 , G06F9/3834 , G06F9/3842 , G06F9/3863 , G06F9/3865
摘要： A method and apparatus for reordering memory operations in superscalar or very long instruction word (VLIW) processors is described, incorporating a mechanism that allows for arbitrary distance between reading from memory and using data loaded out-of-order, and that allows for moving load operations earlier in the execution stream. This mechanism tolerates ambiguous memory references. The mechanism executes only one additional instruction for disambiguation purposes, thus producing good performance, and integrates memory disambiguation with speculative execution of instructions. The overhead introduced is only one instruction, and the load operation can be arbitrarily moved earlier in the instruction stream. The mechanism can cope with conflicts that occur as a result of an unexpected combination of store/load instructions, can be used in a coherent multiprocessor context, and combines speculative execution with reordering of memory operations in a way which requires simple hardware support.
摘要翻译：描述了用于对超标量或非常长指令字（VLIW）处理器中的存储器操作进行重新排序的方法和装置，其包括允许从存储器读取和使用无序加载的数据之间的任意距离的机制，并且允许移动负载执行流中较早的操作。这种机制可以容忍不明确的内存引用。该机制仅执行一个额外的消除歧义的指令，从而产生良好的性能，并将内存消歧与推测性执行指令相结合。所引入的开销只是一条指令，并且加载操作可以在指令流中较早地任意移动。该机制可以解决由于存储/加载指令的意外组合而导致的冲突，可以在一致的多处理器上下文中使用，并且以推荐的执行和对存储器操作的重新排序以需要简单的硬件支持的方式组合。

7. 发明授权

US09632778B2 Gather/scatter of multiple data elements with packed loading/storing into /from a register file entry 有权
公开(公告)号：US09632778B2
公开(公告)日：2017-04-25
申请号：US13569363
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Embodiments relate to packed loading and storing of data. An aspect includes a system for packed loading and storing of distributed data. The system includes memory and a processing element configured to communicate with the memory. The processing element is configured to perform a method including fetching and decoding an instruction for execution by the processing element. A plurality of individually addressable data elements is gathered from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The processing element packs and loads the data elements into register file elements of a register file entry based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.

8. 发明授权

US07870341B2 Cache line replacement techniques allowing choice of LFU or MFU cache line replacement 有权
公开(公告)号：US07870341B2
公开(公告)日：2011-01-11
申请号：US12130245
申请日：2008-05-30
申请人： Richard Edward Matick , Jaime H. Moreno , Malcolm Scott Ware
发明人： Richard Edward Matick , Jaime H. Moreno , Malcolm Scott Ware
IPC分类号： G06F12/12
CPC分类号： H04W12/06 , G06F12/122 , G06F12/127 , H04L63/0853 , Y02D10/13
摘要： Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed. The cache additionally comprises MFU circuitry (1) adapted to produce new state information for the at least two given cache lines in response to an access to one of the at least two given cache lines, and (2) when a cache miss occurs in one of the at least two given cache lines, adapted to determine, based on the new state information, which of the at least two given cache lines is the most frequently used cache line.

9. 发明申请

US20090182951A1 CACHE LINE REPLACEMENT TECHNIQUES ALLOWING CHOICE OF LFU OR MFU CACHE LINE REPLACEMENT 有权
公开(公告)号：US20090182951A1
公开(公告)日：2009-07-16
申请号：US12130245
申请日：2008-05-30
申请人： Richard Edward Matick , Jaime H. Moreno , Malcolm Scott Ware
发明人： Richard Edward Matick , Jaime H. Moreno , Malcolm Scott Ware
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： H04W12/06 , G06F12/122 , G06F12/127 , H04L63/0853 , Y02D10/13
摘要： Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed. The cache additionally comprises MFU circuitry (1) adapted to produce new state information for the at least two given cache lines in response to an access to one of the at least two given cache lines, and (2) when a cache miss occurs in one of the at least two given cache lines, adapted to determine, based on the new state information, which of the at least two given cache lines is the most frequently used cache line.

10. 发明授权

US07051186B2 Selective bypassing of a multi-port register file 失效
标题翻译：选择性绕过多端口寄存器文件
公开(公告)号：US07051186B2
公开(公告)日：2006-05-23
申请号：US10230492
申请日：2002-08-29
申请人： Sameh Asaad , Jaime H. Moreno , Victor Zyuban
发明人： Sameh Asaad , Jaime H. Moreno , Victor Zyuban
IPC分类号： G06F15/82 , G06F9/305
CPC分类号： G06F9/3826 , G06F9/30109
摘要： A multi-port register file may be selectively bypassed such that any element in a result vector is bypassed to the same index of an input vector of a succeeding operation when the element is requested in the succeeding operation in the same index as it was generated. Alternatively, the results to be placed in a register file may be bypassed to a succeeding operation when the N elements that dynamically compose a vector are requested as inputs to the next operation exactly in the same order as they were generated. That is, for the purposes of bypassing, the N vector elements are treated as a single entity. Similar rules apply for the write-through path.
摘要翻译：可以选择性地旁路多端口寄存器文件，使得当在跟随生成的相同索引中在后续操作中请求元素时，结果向量中的任何元素被绕过到后续操作的输入向量的相同索引。或者，当动态组成向量的N个要素作为下一个操作的输入被精确地按照它们被生成的相同顺序被请求作为输入时，放置在寄存器文件中的结果可以被绕过到后续的操作。也就是说，为了绕过，N个向量元素被视为单个实体。类似的规则适用于直通路径。

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