专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09373557B2 Enhanced modularity in heterogeneous 3D stacks 有权
标题翻译：在异构3D堆栈中增强模块化
公开(公告)号：US09373557B2
公开(公告)日：2016-06-21
申请号：US13535675
申请日：2012-06-28
申请人： Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F17/50 , H01L23/14 , H05K3/46 , H01L23/13 , H01L23/538 , H01L25/065 , H01L25/18 , H05K3/30 , H01L21/48
CPC分类号： H01L23/147 , H01L21/4803 , H01L23/13 , H01L23/5382 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2225/06575 , H01L2225/06589 , H01L2924/0002 , H01L2924/15311 , H05K3/30 , H05K3/465 , Y10T29/49128 , Y10T29/4913 , Y10T29/49137 , Y10T29/49146 , H01L2924/00
摘要： A method for generating and implementing a three-dimensional (3D) computer processing chip stack plan that includes receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to a layer in the 3D computer processing chip stack plan. The method also includes identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The method further includes determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment generates and integrates both the layer including the common structures and technologies and the host layer including the uncommon structures and technologies to form the 3D computer processing chip stack.
摘要翻译：一种用于生成和实现三维（3D）计算机处理芯片堆栈计划的方法，其包括从多个客户端接收系统需求，从系统需求中识别公共处理结构和技术，以及将公共处理结构和技术分配给三层计算机处理芯片堆栈计划。该方法还包括从系统需求中识别不常见的处理结构和技术，并将不常见的处理结构和技术分配给3D计算机处理芯片堆栈计划中的主机层。该方法还包括确定主机层上的不常见结构的布置和布线，将布置信息存储在计划中，并将该计划传送到制造设备。制造设备生成并集成了包括公共结构和技术的层，以及主机层，包括不常见的结构和技术，以形成3D计算机处理芯片堆栈。

2. 发明授权

US08595731B2 Low overhead dynamic thermal management in many-core cluster architecture 失效
标题翻译：多核心集群架构中的低开销动态热管理
公开(公告)号：US08595731B2
公开(公告)日：2013-11-26
申请号：US12698545
申请日：2010-02-02
申请人： Pradip Bose , Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Pradip Bose , Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F9/46 , G06F9/44
CPC分类号： G06F9/46
摘要： A semiconductor chip includes a plurality of multi-core clusters each including a plurality of cores and a cluster controller unit. Each cluster controller unit is configured to control thread assignment within the multi-core cluster to which it belongs. The cluster controller unit monitors various parameters measured in the plurality of cores within the multi-core cluster to estimate the computational demand of each thread that runs in the cores. The cluster controller unit may reassign the threads within the multi-core cluster based on the estimated computational demand of the threads and transmit a signal to an upper-level software manager that controls the thread assignment across the semiconductor chip. When an acceptable solution to thread assignment cannot be achieved by shuffling of threads within the multi-core cluster, the cluster controller unit may also report inability to solve thread assignment to the upper-level software manager to request a system level solution.
摘要翻译：半导体芯片包括多个多芯簇，每个多核簇包括多个核和集群控制器单元。每个集群控制器单元被配置为控制它所属的多核集群内的线程分配。集群控制器单元监视在多核集群内的多个核心中测量的各种参数，以估计在核心中运行的每个线程的计算需求。集群控制器单元可以基于线程的估计的计算需求来重新分配多核集群内的线程，并将信号发送到控制半导体芯片上的线程分配的上级软件管理器。当通过在多核心集群内的线程进行混洗，无法实现线程分配的可接受解决方案时，集群控制器单元也可能会报告无法解决线程分配给上级软件管理器以请求系统级解决方案。

3. 发明申请

US20120272202A1 Enhanced Modularity in Heterogeneous 3D Stacks 有权
标题翻译：在异构3D堆栈中增强模块化
公开(公告)号：US20120272202A1
公开(公告)日：2012-10-25
申请号：US13535675
申请日：2012-06-28
申请人： Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F17/50
CPC分类号： H01L23/147 , H01L21/4803 , H01L23/13 , H01L23/5382 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2225/06575 , H01L2225/06589 , H01L2924/0002 , H01L2924/15311 , H05K3/30 , H05K3/465 , Y10T29/49128 , Y10T29/4913 , Y10T29/49137 , Y10T29/49146 , H01L2924/00
摘要： A method for generating and implementing a three-dimensional (3D) computer processing chip stack plan that includes receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to a layer in the 3D computer processing chip stack plan. The method also includes identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The method further includes determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment generates and integrates both the layer including the common structures and technologies and the host layer including the uncommon structures and technologies to form the 3D computer processing chip stack.
摘要翻译：一种用于生成和实现三维（3D）计算机处理芯片堆栈计划的方法，其包括从多个客户端接收系统需求，从系统需求中识别公共处理结构和技术，以及将公共处理结构和技术分配给三层计算机处理芯片堆栈计划。该方法还包括从系统需求中识别不常见的处理结构和技术，并将不常见的处理结构和技术分配给3D计算机处理芯片堆栈计划中的主机层。该方法还包括确定主机层上的不常见结构的布置和布线，将布置信息存储在计划中，并将该计划传送到制造设备。制造设备生成并集成了包括公共结构和技术的层，以及主机层，包括不常见的结构和技术，以形成3D计算机处理芯片堆栈。

4. 发明申请

US20110191776A1 LOW OVERHEAD DYNAMIC THERMAL MANAGEMENT IN MANY-CORE CLUSTER ARCHITECTURE 失效
标题翻译：多个核心集群架构中的低层动态热管理
公开(公告)号：US20110191776A1
公开(公告)日：2011-08-04
申请号：US12698545
申请日：2010-02-02
申请人： Pradip Bose , Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Pradip Bose , Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F9/46
CPC分类号： G06F9/46
摘要： A semiconductor chip includes a plurality of multi-core clusters each including a plurality of cores and a cluster controller unit. Each cluster controller unit is configured to control thread assignment within the multi-core cluster to which it belongs. The cluster controller unit monitors various parameters measured in the plurality of cores within the multi-core cluster to estimate the computational demand of each thread that runs in the cores. The cluster controller unit may reassign the threads within the multi-core cluster based on the estimated computational demand of the threads and transmit a signal to an upper-level software manager that controls the thread assignment across the semiconductor chip. When an acceptable solution to thread assignment cannot be achieved by shuffling of threads within the multi-core cluster, the cluster controller unit may also report inability to solve thread assignment to the upper-level software manager to request a system level solution.
摘要翻译：半导体芯片包括多个多芯簇，每个多核簇包括多个核和集群控制器单元。每个集群控制器单元被配置为控制它所属的多核集群内的线程分配。集群控制器单元监视在多核集群内的多个核心中测量的各种参数，以估计在核心中运行的每个线程的计算需求。集群控制器单元可以基于线程的估计的计算需求来重新分配多核集群内的线程，并将信号发送到控制半导体芯片上的线程分配的上级软件管理器。当通过在多核心集群内的线程进行混洗，无法实现线程分配的可接受解决方案时，集群控制器单元也可能会报告无法解决线程分配给上级软件管理器以请求系统级解决方案。

5. 发明授权

US07921331B2 Write filter cache method and apparatus for protecting the microprocessor core from soft errors 有权
标题翻译：用于保护微处理器内核免受软错误的写入过滤器高速缓存方法和装置
公开(公告)号：US07921331B2
公开(公告)日：2011-04-05
申请号：US12138099
申请日：2008-06-12
申请人： Pradip Bose , Zhigang Hu , Xiaodong Li , Jude A. Rivers
发明人： Pradip Bose , Zhigang Hu , Xiaodong Li , Jude A. Rivers
IPC分类号： G06F11/00 , G06F11/08
CPC分类号： G06F12/0804 , G06F11/1497 , G06F2212/1032
摘要： A write filter cache system for protecting a microprocessor core from soft errors and method thereof are provided. In one aspect, data coming from a processor core to be written in primary cache memory, for instance, L1 cache memory system, is buffered in a write filter cache placed between the primary cache memory and the processor core. The data from the write filter is move to the main cache memory only if it is verified that main thread's data is soft error free, for instance, by comparing the main thread's data with that of its redundant thread. The main cache memory only keeps clean data associated with accepted checkpoints.
摘要翻译：提供了一种用于保护微处理器内核免受软错误的写过滤器高速缓存系统及其方法。在一个方面，来自处理器核心的要写入主高速缓存存储器（例如，L1高速缓存存储器系统）的数据被缓存在放置在主高速缓冲存储器和处理器核心之间的写入过滤器高速缓存中。只有在验证主线程的数据是软错误的情况下，例如通过将主线程的数据与其冗余线程的数据进行比较，才能将写入过滤器的数据移动到主缓存器。主缓存只保留与接受检查点关联的干净数据。

6. 发明申请

US20100333056A1 TEMPERATURE-CONTROLLED 3-DIMENSIONAL BUS PLACEMENT 有权
标题翻译：温度控制三维总线布置
公开(公告)号：US20100333056A1
公开(公告)日：2010-12-30
申请号：US12493599
申请日：2009-06-29
申请人： Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Block placement within each device-containing layer is optimized under the constraint of a simultaneous optimization of interlayer connectivity between the device-containing layer and immediately adjacent device-containing layers. For each functional block within the device-containing layer, lateral heat flow is calculated to laterally adjacent functional blocks. If the lateral heat flow is less than a threshold value for a pair of adjacent functional blocks, placement of the functional blocks and/or interlayer interconnect structure array therebetween or modification of the interlayer interconnect structure array is performed. This routine is repeated for all adjacent pairs of functional blocks in each of the device-containing layers. Subsequently, block placement within each device-containing layer may be optimized under the constraint of a simultaneous optimization of interlayer connectivity across all device-containing layers. This method provides a design having sufficient lateral heat flow in each of the device-containing layers in a semiconductor chip.
摘要翻译：在包含装置的层和紧邻相邻的装置层之间的层间连通性的同时优化的限制下，在每个含有装置的层内的块放置被优化。对于含有装置的层内的每个功能块，横向热流被计算为横向相邻的功能块。如果侧向热流小于一对相邻功能块的阈值，则在其间布置功能块和/或层间互连结构阵列或者修改层间互连结构阵列。对于每个含设备的层中的所有相邻的功能块对，重复此例程。随后，可以在跨所有含有装置的层的层间连接的同时优化的约束下优化在每个包含装置的层内的块放置。该方法提供了在半导体芯片中的每个含有器件的层中具有足够的横向热流的设计。

7. 发明授权

US07076681B2 Processor with demand-driven clock throttling power reduction 失效
标题翻译：处理器采用需求驱动的时钟节流功率降低
公开(公告)号：US07076681B2
公开(公告)日：2006-07-11
申请号：US10187698
申请日：2002-07-02
申请人： Pradip Bose , Daniel M. Citron , Peter W. Cook , Philip G. Emma , Hans M. Jacobson , Prabhakar N. Kudva , Stanley E. Schuster , Jude A. Rivers , Victor V. Zyuban
发明人： Pradip Bose , Daniel M. Citron , Peter W. Cook , Philip G. Emma , Hans M. Jacobson , Prabhakar N. Kudva , Stanley E. Schuster , Jude A. Rivers , Victor V. Zyuban
IPC分类号： G06F1/04
CPC分类号： G06F9/3869 , G06F1/04 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F9/30083 , G06F9/3802 , G06F9/3836 , G06F9/384 , G06F9/3867 , Y02D10/126 , Y02D10/128 , Y02D10/152 , Y02D10/171
摘要： A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.
摘要翻译：同步集成电路，如标量处理器或超标量处理器。电路组件或单元由公共系统时钟计时并同步。至少两个时钟单元包括多个寄存器级，例如流水线级。每个时钟单元中的本地时钟发生器将来自一个或多个其他单元的公共系统时钟和失速状态相结合，以调整寄存器时钟频率向上或向下。

8. 发明授权

US10216557B2 Method and apparatus for monitoring and enhancing on-chip microprocessor reliability 有权
公开(公告)号：US10216557B2
公开(公告)日：2019-02-26
申请号：US12256907
申请日：2008-10-23
申请人： Pradip Bose , Jude A. Rivers , Jayanth Srinivasan
发明人： Pradip Bose , Jude A. Rivers , Jayanth Srinivasan
IPC分类号： G06F11/30 , G21C17/00 , G06F11/00 , G06F11/07
摘要： A system and method for projecting reliability to manage system functions includes an activity module which determines activity in the system. A reliability module interacts with the activity module to determine a reliability measurement for the module in real-time based upon the activity and measured operational quantities of the system. A management module manages actions of the system based upon the reliability measurement input from the reliability module. This may be to provide corrective action, to reallocate resources, or increase reliability of the module.

9. 发明授权

US08589762B2 Adaptive multi-bit error correction in endurance limited memories 失效
标题翻译：耐力有限的存储器中的自适应多位错误校正
公开(公告)号：US08589762B2
公开(公告)日：2013-11-19
申请号：US13176092
申请日：2011-07-05
申请人： Jude A. Rivers , Vijayalakshmi Srinivasan
发明人： Jude A. Rivers , Vijayalakshmi Srinivasan
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G06F11/1048 , G11C16/3418 , G11C29/028 , G11C2029/0409 , G11C2029/0411
摘要： Multi-bit stuck-at fault error recovery can be enabled by adaptive multi-bit error correction method, in which the overhead of error correction hardware is reduced without affecting the lifetime of the memory device. Error correction logic hardware is decoupled from memory blocks. An error correction logic block is partitioned such that error correction logic entries support different number of error correction capabilities based on the probability of occurrence of the different number of errors in different memory blocks. Faulty memory blocks are mapped to appropriate error correction logic entries. The mapping can be one-to-one or many-to-one depending on embodiments. The adaptive partitioning of the error correction logic entries can be configured to match projected statistical distribution of errors in logic blocks, and can reduce the total error correction logic overhead, provide sufficient error correction, and/or extend the lifetime of the memory device.
摘要翻译：可以通过自适应多位错误校正方法来实现多位卡滞故障恢复，其中降低了纠错硬件的开销，而不影响存储器件的使用寿命。纠错逻辑硬件与存储器块分离。错误校正逻辑块被分区，使得纠错逻辑条目基于在不同存储器块中出现不同数量的错误的概率来支持不同数量的纠错能力。错误的存储器块被映射到适当的纠错逻辑条目。取决于实施例，映射可以是一对一或多对一。错误校正逻辑条目的自适应分割可以被配置为匹配逻辑块中的误差的预计统计分布，并且可以减少总误差校正逻辑开销，提供足够的纠错和/或延长存储器件的寿命。

10. 发明授权

US08589662B2 Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signals 失效
标题翻译：基于比较预测和实际相关性控制信号来接受或回滚指令的执行
公开(公告)号：US08589662B2
公开(公告)日：2013-11-19
申请号：US13371181
申请日：2012-02-10
申请人： Erik R. Altman , Michael K. Gschwind , Jude A. Rivers , Sumedh W. Sathaye , John-David Wellman , Victor V. Zyuban
发明人： Erik R. Altman , Michael K. Gschwind , Jude A. Rivers , Sumedh W. Sathaye , John-David Wellman , Victor V. Zyuban
IPC分类号： G06F9/30
CPC分类号： G06F9/3808 , G06F9/3838 , G06F9/3859 , G06F9/3873
摘要： A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.
摘要翻译：在微处理器管线的各个阶段提供动态预测和/或精确缓存机制，使得可以在程序执行过程中存储和存储各种控制信号。精确的控制信号矢量缓存可以完成。每当在指令解码，注册重命名和依赖关系检查之后形成问题组时，可以在引导指令的标签下缓存问题组信息的编码副本。所产生的依赖性高速缓存或控制向量高速缓存可以在微处理器流水线的指令发出逻辑阶段的开始时被下一次相应的指令组出现以重新执行。由于可以在高速缓存中的单个周期中访问编码的问题组位模式，所以具有该实施例的所得微处理器流水线可以被看作是两个并行的管道，其中如果存在依赖性高速缓存或控制向量高速缓存击中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式