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1. 发明授权

US5625835A Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor 失效
标题翻译：用于在超标量或非常长的指令字处理器中重新排序存储器操作的方法和装置
公开(公告)号：US5625835A
公开(公告)日：1997-04-29
申请号：US435411
申请日：1995-05-10
申请人： Mahmut K. Ebcioglu , David A. Luick , Jaime H. Moreno , Gabriel M. Silberman , Philip B. Winterfield
发明人： Mahmut K. Ebcioglu , David A. Luick , Jaime H. Moreno , Gabriel M. Silberman , Philip B. Winterfield
IPC分类号： G06F9/38
CPC分类号： G06F9/383 , G06F9/30043 , G06F9/3834 , G06F9/3842 , G06F9/3863 , G06F9/3865
摘要： A method and apparatus for reordering memory operations in superscalar or very long instruction word (VLIW) processors is described, incorporating a mechanism that allows for arbitrary distance between reading from memory and using data loaded out-of-order, and that allows for moving load operations earlier in the execution stream. This mechanism tolerates ambiguous memory references. The mechanism executes only one additional instruction for disambiguation purposes, thus producing good performance, and integrates memory disambiguation with speculative execution of instructions. The overhead introduced is only one instruction, and the load operation can be arbitrarily moved earlier in the instruction stream. The mechanism can cope with conflicts that occur as a result of an unexpected combination of store/load instructions, can be used in a coherent multiprocessor context, and combines speculative execution with reordering of memory operations in a way which requires simple hardware support.
摘要翻译：描述了用于对超标量或非常长指令字（VLIW）处理器中的存储器操作进行重新排序的方法和装置，其包括允许从存储器读取和使用无序加载的数据之间的任意距离的机制，并且允许移动负载执行流中较早的操作。这种机制可以容忍不明确的内存引用。该机制仅执行一个额外的消除歧义的指令，从而产生良好的性能，并将内存消歧与推测性执行指令相结合。所引入的开销只是一条指令，并且加载操作可以在指令流中较早地任意移动。该机制可以解决由于存储/加载指令的意外组合而导致的冲突，可以在一致的多处理器上下文中使用，并且以推荐的执行和对存储器操作的重新排序以需要简单的硬件支持的方式组合。

2. 发明授权

US4763289A Method for the modeling and fault simulation of complementary metal oxide semiconductor circuits 失效
标题翻译：互补金属氧化物半导体电路的建模和故障模拟方法
公开(公告)号：US4763289A
公开(公告)日：1988-08-09
申请号：US815435
申请日：1985-12-31
申请人： Zeev Barzilai , Vijay S. Iyengar , Barry K. Rosen , Gabriel M. Silberman
发明人： Zeev Barzilai , Vijay S. Iyengar , Barry K. Rosen , Gabriel M. Silberman
IPC分类号： G01R31/302 , G01R31/3183 , G06F11/25 , G06F17/50 , G06F15/20 , G06F11/22
CPC分类号： G01R31/318357 , G01R31/3183 , G06F17/5022
摘要： A method for modeling complementary metal oxide semiconductor (CMOS) combinatorial logic circuits by Boolean gates taking into account circuit behavior effects due to charge storing and static hazards. Models are developed for both the faultless and faulty operation of each circuit. According to a further aspect of the invention, these models are used in a simulation procedure to evaluate the fault coverage of a large scale integrated circuit design built using a plurality of these circuits. In the evaluation procedure the faulty model is used only for a particular circuit whose failure performance is being tested and the faultless model is utilized for all other circuits. This procedure is continued until all of the individual gate circuits have been evaluated.
摘要翻译：考虑由于电荷存储和静电危害引起的电路行为影响，通过布尔门对互补金属氧化物半导体（CMOS）组合逻辑电路进行建模的方法。模型是为每个电路的无故障和故障运行而开发的。根据本发明的另一方面，这些模型用于模拟过程中以评估使用多个这些电路构建的大规模集成电路设计的故障覆盖。在评估过程中，故障模型仅用于正在测试其故障性能的特定电路，并且所有其他电路都使用无故障模型。该过程继续进行，直到所有单独的门电路都被评估为止。

3. 发明授权

US4698830A Shift register latch arrangement for enhanced testability in differential cascode voltage switch circuit 失效
标题翻译：移位寄存器锁存装置，用于提高差分共源共栅电压开关电路的可测试性
公开(公告)号：US4698830A
公开(公告)日：1987-10-06
申请号：US850189
申请日：1986-04-10
申请人： Zeev Barzilai , Vijay S. Iyengar , Gabriel M. Silberman
发明人： Zeev Barzilai , Vijay S. Iyengar , Gabriel M. Silberman
IPC分类号： G06F11/22 , G01R31/28 , G01R31/3185 , H03K19/173 , G11C29/00
CPC分类号： G01R31/318541 , G01R31/318547 , H03K19/1738
摘要： A shift register latch (SRL) arrangement for testing a combinational logic circuit, producing true and complement outputs in nature, has two clocked DC latches and additional circuitry for providing an input to the second latch. Clock signal trains and an extra TEST signal are used to control the SRL arrangement in different modes. In a first mode, one of the outputs from the combinational logic circuit is latched into the first latch and provided to a succeeding combinational logic circuit. In a second mode, a plurality of the SRL arrangements are interconnected together to form a shift register chain so that each latch acts as one position of the shift register chain. Further, in a third mode, the true and complement outputs of the combinational logic circuit are exclusive ORed and its result is latched into the second latch. During the third mode, output of the first latch is prevented from being latched into the second latch.
摘要翻译：用于测试组合逻辑电路的移位寄存器锁存（SRL）装置本质上产生真实和补码输出具有两个时钟直流锁存器和用于向第二锁存器提供输入的附加电路。时钟信号列和额外的TEST信号用于控制不同模式下的SRL布局。在第一模式中，来自组合逻辑电路的输出之一被锁存到第一锁存器中并提供给后续的组合逻辑电路。在第二模式中，多个SRL装置互连在一起以形成移位寄存器链，使得每个锁存器用作移位寄存器链的一个位置。此外，在第三模式中，组合逻辑电路的真和补输出是异或运算，其结果被锁存到第二锁存器中。在第三模式期间，防止第一锁存器的输出被锁存到第二锁存器中。

4. 发明授权

US4727313A Fault simulation for differential cascode voltage switches 失效
标题翻译：差分共源共栅电压开关的故障模拟
公开(公告)号：US4727313A
公开(公告)日：1988-02-23
申请号：US709612
申请日：1985-03-08
申请人： Zeev Barazilai , Vijay S. Iyengar , Barry K. Rosen , Gabriel M. Silberman
发明人： Zeev Barazilai , Vijay S. Iyengar , Barry K. Rosen , Gabriel M. Silberman
IPC分类号： G01R31/28 , G06F11/26 , G06F17/50
CPC分类号： G06F17/5022 , G06F11/261
摘要： A method of simulating a differential cascode voltage switch circuit (domino circuit) by replacing each switch-level logic tree by a three-section Boolean tree. In each section, a switch is replaced by an AND gate. The first and third section pass signals in one direction and the second section passes signals in the opposite directions. The three sections are interconnected end to end. Various faults can be simulated by holding selected internal signals at faulty values.
摘要翻译：通过用三段布尔树替换每个开关级逻辑树，来模拟差分共源共栅电压开关电路（domino circuit）的方法。在每个部分中，开关由AND门代替。第一和第三部分在一个方向上传递信号，而第二部分在相反的方向上传递信号。这三个部分是端对端互连的。可以通过保持所选内部信号的故障值来模拟各种故障。

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