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1. 发明授权

US06711651B1 Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetching 有权
标题翻译：用于使用推取预取的多处理器系统的相干高速缓冲存储器中共享数据的基于历史的移动的方法和装置
公开(公告)号：US06711651B1
公开(公告)日：2004-03-23
申请号：US09655642
申请日：2000-09-05
申请人： Jaime H. Moreno , Jude A. Rivers , John-David Wellman
发明人： Jaime H. Moreno , Jude A. Rivers , John-David Wellman
IPC分类号： G06F1300
CPC分类号： G06F12/0862 , G06F12/0815 , G06F2212/6024
摘要： A method and apparatus are provided for moving at least one of instructions and operand data throughout a plurality of caches included in a multiprocessor computer system, wherein each of the plurality of caches is included in one of a plurality of processing nodes of the system so as to provide history-based movement of shared-data in coherent cache memories. A plurality of entries are stored in a consume after produce (CAP) table attached to each of the plurality of caches. Each of the entries is associated with a plurality of storage elements in one of the plurality of caches and includes information of prior usage of the plurality of storage elements by each of the plurality of processing nodes. Upon a miss by a processing node to a cache included therein, any storage elements that caused the miss are transferred to the cache from one of main memory and another cache. An entry is created in the table that is associated with the storage elements that caused the miss. A push prefetching engine may be used to create the entry.
摘要翻译：提供了一种方法和装置，用于在包括在多处理器计算机系统中的多个高速缓存中移动指令和操作数数据中的至少一个，其中多个高速缓存中的每一个包括在系统的多个处理节点之一中，以便以共享缓存存储器中的共享数据提供基于历史的移动。在附加到多个高速缓存中的每一个的产生（CAP）表之后，将多个条目存储在消费中。每个条目与多个高速缓存之一中的多个存储元件相关联，并且包括多个处理节点中的每一个的多个存储元件的先前使用的信息。当处理节点错过其中包含的高速缓存时，导致未命中的任何存储元件从主存储器和另一高速缓存之一传送到高速缓存。在表中创建一个与导致未命中的存储元素相关联的条目。推式预取引擎可用于创建条目。

2. 发明授权

US07130963B2 System and method for instruction memory storage and processing based on backwards branch control information 失效
标题翻译：基于向后分支控制信息的指令存储器和处理系统和方法
公开(公告)号：US07130963B2
公开(公告)日：2006-10-31
申请号：US10620734
申请日：2003-07-16
申请人： Sameh W. Asaad , Jaime H. Moreno , Jude A. Rivers , John-David Wellman
发明人： Sameh W. Asaad , Jaime H. Moreno , Jude A. Rivers , John-David Wellman
IPC分类号： G06F12/00
CPC分类号： G06F9/381
摘要： A system for instruction memory storage and processing in a computing device having a processor, the system is based on backwards branch control information and comprises a dynamic loop buffer (DLB) which is a tagless array of data organized as a direct-mapped structure; a DLB controller having a primary memory unit partitioned into a plurality of banks for controlling the state of the instruction memory system and accepting a program counter address as an input, the DLB controller outputs distinct signals. The system further comprises an address register located in the memory of the computing device, it is a staging register for the program counter address and an instruction fetch process that takes two cycles of the processor clock; and a bank select unit for serving as a program counter address decoder to accept the program counter address and to output a bank enable signal for selecting a bank in a primary memory unit, and a decoded address for access within the selected bank.
摘要翻译：一种用于具有处理器的计算设备中的指令存储器存储和处理的系统，所述系统基于向后分支控制信息，并且包括动态循环缓冲器（DLB），其是被组织为直接映射结构的无标记数据阵列; DLB控制器具有划分为多个存储体的主存储器单元，用于控制指令存储器系统的状态并接受程序计数器地址作为输入，DLB控制器输出不同的信号。该系统还包括位于计算设备的存储器中的地址寄存器，它是用于程序计数器地址的分段寄存器和执行处理器时钟的两个周期的指令获取处理; 以及用于作为程序计数器地址解码器接受程序计数器地址并输出用于选择主存储器单元中的存储体的存储体使能信号的存储体选择单元和在所选择的存储体内的存取的解码地址。

3. 发明授权

US06678795B1 Method and apparatus for memory prefetching based on intra-page usage history 有权
标题翻译：基于页内使用历史记录预取的方法和装置
公开(公告)号：US06678795B1
公开(公告)日：2004-01-13
申请号：US09639263
申请日：2000-08-15
申请人： Jaime H. Moreno , Jude A. Rivers , John-David Wellman
发明人： Jaime H. Moreno , Jude A. Rivers , John-David Wellman
IPC分类号： G06F1208
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： There is provided a method for fetching at least one of instructions and operand data from a second memory into a first memory of a computer system having at least one processor. The method includes the step of storing a plurality of entries in a table associated with the first memory. Each entry is associated with a memory page that includes a plurality of storage elements in the second memory, and includes information of prior access by the at least one processor to each of the plurality of storage elements. Upon a miss to the first memory from the at least one processor based upon a request, the table is searched for a given entry associated with a given page that includes a target of the request. If the given entry is found, then at least one prefetch request is generated to fetch at least one storage element included in the given page from the second memory to the first memory, based upon given information comprised in the given entry.
摘要翻译：提供了一种用于将指令和操作数中的至少一个从第二存储器读取到具有至少一个处理器的计算机系统的第一存储器中的方法。该方法包括将多个条目存储在与第一存储器相关联的表中的步骤。每个条目与包括第二存储器中的多个存储元件的存储器页面相关联，并且包括至少一个处理器对多个存储元件中的每一个的先前访问的信息。在基于请求错过从至少一个处理器到第一存储器时，搜索与包括请求的目标的给定页面相关联的给定条目的表。如果找到给定条目，则基于给定条目中包含的给定信息，生成至少一个预取请求以从包含在给定页面中的至少一个存储元件从第二存储器提取到第一存储器。

4. 发明授权

US06948051B2 Method and apparatus for reducing logic activity in a microprocessor using reduced bit width slices that are enabled or disabled depending on operation width 失效
标题翻译：使用减少的位宽度切片减少微处理器中的逻辑活动的方法和装置，其根据操作宽度被启用或禁用
公开(公告)号：US06948051B2
公开(公告)日：2005-09-20
申请号：US09855241
申请日：2001-05-15
申请人： Jude A. Rivers , Jaime H. Moreno , Vinodh R. Cuppu
发明人： Jude A. Rivers , Jaime H. Moreno , Vinodh R. Cuppu
IPC分类号： G06F9/30 , G06F9/302 , G06F9/38 , G06F9/318
CPC分类号： G06F9/3891 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/3016 , G06F9/30192 , G06F9/3887
摘要： A method and apparatus for reducing logic activity in a microprocessor which examines every instruction before it is executed and determines in advance the minimum appropriate datapath width (in byte or half-word quantities) necessary to accurately execute the operation. Achieving this requires two major enhancements to a traditional microprocessor pipeline. First, extra logic (potentially an extra pipeline stage for determining an operation's effective bit width—the WD width detection logic) is introduced between the Decode and Execution stages. Second, the traditional Execution stage architecture (including a register file RF and the arithmetic logical unit ALU), instead of being organized as one continuous 32-bit unit, is organized as a collection of multiple slices, where a slice can be of an 8-bit (a byte) or a 16-bit (double byte) granularity. Each slice in this case can operate independently of each other slice, and includes portion of the register file, functional unit and cache memory. Concatenating a multiple number of these slices together creates a required full width processor.
摘要翻译：一种用于减少微处理器中的逻辑活动的方法和装置，其在执行之前检查每个指令，并且预先确定准确执行该操作所需的最小适当的数据路径宽度（以字节或半字数量）。实现这一点需要对传统微处理器管道进行两个主要的改进。首先，在解码和执行阶段之间引入额外的逻辑（潜在的用于确定操作的有效位宽度的额外流水线级 - WD宽度检测逻辑）。第二，传统的执行阶段架构（包括寄存器文件RF和算术逻辑单元ALU）而不是组织为一个连续的32位单元，被组织为多个片段的集合，其中片可以是8 位（一个字节）或一个16位（双字节）粒度。在这种情况下，每个切片可独立于每个切片进行操作，并且包括寄存器文件，功能单元和高速缓冲存储器的部分。将多个这些切片连接在一起创建所需的全宽处理器。

5. 发明申请

US20120144166A1 CONTROL SIGNAL MEMOIZATION IN A MULTIPLE INSTRUCTION ISSUE MICROPROCESSOR 失效
标题翻译：多指令问题微处理器中的控制信号记录
公开(公告)号：US20120144166A1
公开(公告)日：2012-06-07
申请号：US13371181
申请日：2012-02-10
申请人： Erik Richter Altman , Michael Karl Gschwind , Jude A. Rivers , Sumedh W. Sathaye , John-David Wellman , Victor V. Zyuban
发明人： Erik Richter Altman , Michael Karl Gschwind , Jude A. Rivers , Sumedh W. Sathaye , John-David Wellman , Victor V. Zyuban
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3808 , G06F9/3838 , G06F9/3859 , G06F9/3873
摘要： A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.
摘要翻译：在微处理器管线的各个阶段提供动态预测和/或精确缓存机制，使得可以在程序执行过程中存储和存储各种控制信号。精确的控制信号矢量缓存可以完成。每当在指令解码，注册重命名和依赖关系检查之后形成问题组时，可以在引导指令的标签下缓存问题组信息的编码副本。所产生的依赖性高速缓存或控制向量高速缓存可以在微处理器流水线的指令发出逻辑阶段的开始时被下一次相应的指令组出现以重新执行。由于可以在高速缓存中的单个周期中访问编码的问题组位模式，所以具有该实施例的所得微处理器流水线可以被看作是两个并行管道，其中如果存在依赖性高速缓存或控制向量高速缓冲存储器击中。

6. 发明授权

US07461209B2 Transient cache storage with discard function for disposable data 有权
标题翻译：用于一次性数据的具有丢弃功能的瞬态缓存存储
公开(公告)号：US07461209B2
公开(公告)日：2008-12-02
申请号：US11295300
申请日：2005-12-06
申请人： Erik R. Altman , Michael Karl Gschwind , Robert Kevin Montoye , Jude A. Rivers , Sumedh Wasudeo Sathaye , John-David Wellman , Victor Zyuban
发明人： Erik R. Altman , Michael Karl Gschwind , Robert Kevin Montoye , Jude A. Rivers , Sumedh Wasudeo Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F12/12
CPC分类号： G06F12/1491 , G06F9/3808 , G06F9/3844 , G06F12/0802 , G06F12/0804 , G06F12/12
摘要： A method and apparatus for storing non-critical processor information without imposing significant costs on a processor design is disclosed. Transient data are stored in the processor-local cache hierarchy. An additional control bit forms part of cache addresses, where addresses having the control bit set are designated as “transient storage addresses.” Transient storage addresses are not written back to external main memory and, when evicted from the last level of cache, are discarded. Preferably, transient storage addresses are “privileged” in that they are either not accessible to software or only accessible to supervisory or administrator-level software having appropriate permissions. A number of management functions/instructions are provided to allow administrator/supervisor software to manage and/or modify the behavior of transient cache storage. This transient storage scheme allows the cache hierarchy to store data items that may be used by the processor core but that may be too expensive to allocate to external memory.
摘要翻译：公开了一种用于存储非关键处理器信息而不对处理器设计造成重大成本的方法和装置。瞬态数据存储在处理器本地缓存层次结构中。附加控制位构成高速缓存地址的一部分，其中具有控制位置位的地址被指定为“瞬时存储地址”。瞬态存储地址不会被写回外部主存储器，而当从最后一级高速缓存驱逐时，它们将被丢弃。优选地，瞬态存储地址是“特权的”，因为它们不能被软件访问或只能具有具有适当权限的监督或管理员级软件访问。提供了许多管理功能/指令，以允许管理员/管理软件管理和/或修改瞬态缓存存储的行为。这种瞬态存储方案允许高速缓存层级来存储处理器核心可能使用的数据项，但是可能太昂贵以分配给外部存储器。

7. 发明申请

US20100083203A1 Modeling System-Level Effects of Soft Errors 有权
标题翻译：软错误的系统级效应建模
公开(公告)号：US20100083203A1
公开(公告)日：2010-04-01
申请号：US12243427
申请日：2008-10-01
申请人： Pradip Bose , Prabhakar N. Kudva , Jude A. Rivers , Pia N. Sanda , John-David Wellman
发明人： Pradip Bose , Prabhakar N. Kudva , Jude A. Rivers , Pia N. Sanda , John-David Wellman
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.
摘要翻译：提供了对软错误的系统级别影响进行建模的机制。提供了在IC设计的概念阶段将器件级和组件级软错误率（SER）分析机制与微架构级性能分析工具集成的机制，从而生成SER分析工具。通过将SER分析工具应用于IC设计，可以生成IC设计的第一个SER简档。在IC设计的后期阶段，获得关于IC设计中逻辑和存储元件的SER漏洞的详细信息，并且基于关于SER漏洞的详细信息来改进第一SER简档，从而为IC生成第二SER简档设计。基于第一SER简档或第二SER简档中的一个，在IC设计的一个或多个阶段进行对IC设计的修改。

8. 发明授权

US08589662B2 Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signals 失效
标题翻译：基于比较预测和实际相关性控制信号来接受或回滚指令的执行
公开(公告)号：US08589662B2
公开(公告)日：2013-11-19
申请号：US13371181
申请日：2012-02-10
申请人： Erik R. Altman , Michael K. Gschwind , Jude A. Rivers , Sumedh W. Sathaye , John-David Wellman , Victor V. Zyuban
发明人： Erik R. Altman , Michael K. Gschwind , Jude A. Rivers , Sumedh W. Sathaye , John-David Wellman , Victor V. Zyuban
IPC分类号： G06F9/30
CPC分类号： G06F9/3808 , G06F9/3838 , G06F9/3859 , G06F9/3873
摘要： A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.
摘要翻译：在微处理器管线的各个阶段提供动态预测和/或精确缓存机制，使得可以在程序执行过程中存储和存储各种控制信号。精确的控制信号矢量缓存可以完成。每当在指令解码，注册重命名和依赖关系检查之后形成问题组时，可以在引导指令的标签下缓存问题组信息的编码副本。所产生的依赖性高速缓存或控制向量高速缓存可以在微处理器流水线的指令发出逻辑阶段的开始时被下一次相应的指令组出现以重新执行。由于可以在高速缓存中的单个周期中访问编码的问题组位模式，所以具有该实施例的所得微处理器流水线可以被看作是两个并行的管道，其中如果存在依赖性高速缓存或控制向量高速缓存击中。

9. 发明授权

US07496733B2 System and method of execution of register pointer instructions ahead of instruction issues 有权
标题翻译：提前执行寄存器指针指令的系统和方法问题
公开(公告)号：US07496733B2
公开(公告)日：2009-02-24
申请号：US11924977
申请日：2007-10-26
申请人： Erik Altman , Michael Karl Gschwind , Jude A. Rivers , Sumedh Wasudeo Sathaye , John-David Wellman , Victor Zyuban
发明人： Erik Altman , Michael Karl Gschwind , Jude A. Rivers , Sumedh Wasudeo Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30036 , G06F9/3013 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F9/3885
摘要： A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.
摘要翻译：管道系统和方法包括多个操作阶段。这些阶段包括存储指针信息和更新的指针寄存器阶段，以及位于指针寄存器阶段下游的重命名和依赖性检查阶段，其重新命名寄存器并确定是否存在相关性。功能单元向指针寄存器阶段提供指针信息更新，使得指针信息在寄存器依赖性检查之前或与寄存器依赖性检查并行地更新到指针寄存器阶段。

10. 发明授权

US07325124B2 System and method of execution of register pointer instructions ahead of instruction issue 有权
标题翻译：提前执行寄存器指针指令的系统和方法问题
公开(公告)号：US07325124B2
公开(公告)日：2008-01-29
申请号：US10828794
申请日：2004-04-21
申请人： Erik Altman , Michael Karl Gschwind , Jude A. Rivers , Sumedh Wasudeo Sathaye , John-David Wellman , Victor Zyuban
发明人： Erik Altman , Michael Karl Gschwind , Jude A. Rivers , Sumedh Wasudeo Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30036 , G06F9/3013 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F9/3885
摘要： A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.
摘要翻译：管道系统和方法包括多个操作阶段。这些阶段包括存储指针信息和更新的指针寄存器阶段，以及位于指针寄存器阶段下游的重命名和依赖性检查阶段，其重新命名寄存器并确定是否存在相关性。功能单元向指针寄存器阶段提供指针信息更新，使得指针信息在寄存器依赖性检查之前或与寄存器依赖性检查并行地更新到指针寄存器阶段。

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