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1. 发明授权

US06766440B1 Microprocessor with conditional cross path stall to minimize CPU cycle time length 有权
标题翻译：具有条件交叉路径失速的微处理器，以最小化CPU周期时间长度
公开(公告)号：US06766440B1
公开(公告)日：2004-07-20
申请号：US09702453
申请日：2000-10-31
申请人： Donald E. Steiss , David Hoyle
发明人： Donald E. Steiss , David Hoyle
IPC分类号： G06F930
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3828 , G06F9/3891
摘要： A digital system is provided that includes a central processing unit (CPU) that has an instruction execution pipeline with a plurality of functional units for executing instructions in a sequence of CPU cycles. The execution units are clustered into two or more groups. Cross-path circuitry is provided such that results from any execution unit in one execution unit cluster can be supplied to execution units in another cluster. A cross-path stall is conditionally inserted to stall all of the functional groups when one execution unit cluster requires an operand from another cluster on a given CPU cycle and the execution unit that is producing that operand completes the computation of that operand on an immediately preceding CPU cycle.
摘要翻译：提供了一种数字系统，其包括具有指令执行流水线的中央处理单元（CPU），所述指令执行流水线具有用于以CPU周期的顺序执行指令的多个功能单元。执行单元被分组成两个或更多个组。提供交叉路径电路，使得可以将一个执行单元集群中的任何执行单元的结果提供给另一个集群中的执行单元。当一个执行单元集群在给定的CPU周期中需要来自另一个集群的操作数时，有条件地插入一个跨路径停顿来停止所有的功能组，并且正在产生该操作数的执行单元完成该操作数的计算。 CPU周期。

2. 发明授权

US06760836B2 Apparatus for issuing an instruction to a suitable issue destination 有权
标题翻译：具有向适当发行目的地发出指令的发行控制电路的装置
公开(公告)号：US06760836B2
公开(公告)日：2004-07-06
申请号：US09797734
申请日：2001-03-05
申请人： Mikio Hondou
发明人： Mikio Hondou
IPC分类号： G06F930
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/384
摘要： An instruction issuing device comprises a plurality of issue controlling circuits which run in parallel, and perform a control for preferentially issuing an instruction to a particular arithmetic unit. An optimum issue controlling circuit is selected according to the empty quantity of instruction slots for each arithmetic unit or a result of learning of the number of previously issued instructions, and an issue destination is determined based on the direction of the selected circuit.
摘要翻译：指令发布装置包括并行运行的多个发行控制电路，并且执行用于优先向特定算术单元发出指令的控制。根据每个运算单元的指示槽的空闲量或先前发出的指令的数量的学习结果来选择最佳的问题控制电路，并且基于所选择的电路的方向来确定发布目的地。

3. 发明授权

US06745320B1 Data processing apparatus 失效
标题翻译：数据处理装置
公开(公告)号：US06745320B1
公开(公告)日：2004-06-01
申请号：US09559571
申请日：2000-04-28
申请人： Naoki Mitsuishi
发明人： Naoki Mitsuishi
IPC分类号： G06F930
CPC分类号： G06F9/30138 , G06F9/30014 , G06F9/30101 , G06F9/30112 , G06F9/30185 , G06F9/30189 , G06F9/342
摘要： There is provided a data processing apparatus capable of increasing a number of general purpose registers while maintaining upper compatibility. Register designating information for designating a register is divided in two portions. The two portions are arranged in separate basic units on the basic units of an instruction code. When one instruction code is made ignorable and the ignorable instruction code is ignored, a control unit (CONT) executes register selecting operation by implicitly assuming predetermined register designating information. Thereby, when only a general purpose register (existing general purpose register) capable of being designated implicitly is used, the ignorable instruction code can be ignored and accordingly, the instruction codes are not increased. When an at least conventionally equivalent general purpose register is used, a conventionally equivalent instruction code may be used. By preventing the instruction codes from increasing, processing speed is not reduced.
摘要翻译：提供了一种能够增加多个通用寄存器同时保持较高兼容性的数据处理装置。用于指定寄存器的寄存器指定信息分为两部分。这两个部分在指令代码的基本单元上分开设置。当忽略一个指令代码并忽略可忽略的指令代码时，控制单元（CONT）通过隐含地假设预定的寄存器指定信息来执行寄存器选择操作。因此，当仅使用能够被隐含地指定的通用寄存器（现有通用寄存器）时，可以忽略可忽略的指令代码，因此指令代码不增加。当使用至少传统上等效的通用寄存器时，可以使用传统上等效的指令代码。通过防止指令代码增加，处理速度不降低。

4. 发明授权

US06738792B1 Parallel mask generator 失效
标题翻译：并行面罩发生器
公开(公告)号：US06738792B1
公开(公告)日：2004-05-18
申请号：US09802673
申请日：2001-03-09
申请人： Karthikeyan Muthusamy
发明人： Karthikeyan Muthusamy
IPC分类号： G06F930
CPC分类号： G06F9/30018
摘要： A mask generator circuit includes at least first and second mask generator circuits coupled to receive most significant and least significant sections of the pointer and to generate masks therefrom, and a plurality of circuits each configured to generate a region of the output mask from the mask generator circuit. The mask generated from the most significant bits section of the pointer (the most significant bits (MSB) mask) includes bits corresponding to various regions of the output mask. The plurality of circuits receive the MSB mask and the least significant bits (LSB) mask generated from the least significant bits section of the pointer and generate the output mask therefrom.
摘要翻译：掩模发生器电路包括至少第一和第二掩模发生器电路，其耦合以接收指针的最高有效部分和最不重要的部分并从其生成掩模;以及多个电路，每个电路被配置为从掩模发生器产生输出掩模的区域电路。从指针的最高有效位部分（最高有效位（MSB）掩码）生成的掩码）包括与输出掩码的各个区域对应的位。多个电路接收从指针的最低有效位部分生成的MSB掩码和最低有效位（LSB）掩码，并从其生成输出掩码。

5. 发明授权

US06735685B1 System and method for handling load and/or store operations in a superscalar microprocessor 失效
标题翻译：用于在超标量微处理器中处理负载和/或存储操作的系统和方法
公开(公告)号：US06735685B1
公开(公告)日：2004-05-11
申请号：US09336589
申请日：1999-06-21
申请人： Cheryl D. Senter , Johannes Wang
发明人： Cheryl D. Senter , Johannes Wang
IPC分类号： G06F930
CPC分类号： G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load/store unit is provided whose main purpose is to make load requests out-of-order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out-of-order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load/store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.
摘要翻译：本发明提供一种用于管理在超标量RISC架构环境中读取和写入存储器或I / O所需的负载和存储操作的系统和方法。为了执行此任务，提供了一个加载/存储单元，其主要目的是使可能的负载请求无序地尽可能快地获得负载数据以供指令执行单元使用。如果没有地址冲突，没有写入，只能执行加载操作。当在较旧的指令写入的存储器位置请求读取时，发生地址冲突。写入挂起是指较旧的指令请求存储操作，但存储地址尚未计算的情况。数据高速缓存单元返回8字节的未对齐数据。加载/存储单元在返回指令执行单元之前将其正确对齐。因此，加载/存储单元的三个主要任务是：（1）处理无序缓存请求; （2）检测地址冲突; 和（3）数据对齐。

6. 发明授权

US06718458B2 Method and apparatus for performing addressing operations in a superscalar, superpipelined processor 有权
标题翻译：用于在超标量超级流水线处理器中执行寻址操作的方法和装置
公开(公告)号：US06718458B2
公开(公告)日：2004-04-06
申请号：US10401170
申请日：2003-03-27
申请人： Dan Dobberpuhl , Robert Stepanian
发明人： Dan Dobberpuhl , Robert Stepanian
IPC分类号： G06F930
CPC分类号： G06F9/3873 , G06F9/30167 , G06F9/3836 , G06F9/3867 , G06F9/3885
摘要： A method and apparatus for improving the performance of a superscalar, superpipelined processor by identifying and processing instructions for performing addressing operations is provided. The invention heuristically determines instructions likely to perform addressing operations and assigns those instructions to specialized pipes in a pipeline structure. The invention can assign such instructions to both an execute pipe and a load/store pipe to avoid the occurrence of “bubbles” in the event execution of the instruction requires the calculation capability of the execute pipe. The invention can also examine a sequence of instructions to identify an instruction for performing a calculation where the result of the calculation is used by a succeeding load or store instruction. In this case, the invention controls the pipeline to assure the result of the calculation is available for the succeeding load or store instruction even if both instructions are being processed concurrently.
摘要翻译：提供了一种用于通过识别和处理用于执行寻址操作的指令来改进超标量超管道处理器的性能的方法和装置。本发明启发式地确定可能执行寻址操作的指令，并将这些指令分配给管道结构中的专用管道。本发明可以将这样的指令分配给执行管道和加载/存储管道，以在执行指令需要执行管道的计算能力的情况下避免“气泡”的发生。本发明还可以检查用于识别用于执行计算的指令的指令序列，其中由后续加载或存储指令使用计算结果。在这种情况下，即使两个指令被同时处理，本发明控制流水线以确保计算结果可用于后续的加载或存储指令。

7. 发明授权

US06681319B1 Dual access instruction and compound memory access instruction with compatible address fields 有权
标题翻译：双访问指令和具有兼容地址字段的复合存储器访问指令
公开(公告)号：US06681319B1
公开(公告)日：2004-01-20
申请号：US09410653
申请日：1999-10-01
申请人： Karim Djafarian , Gilbert Laurenti , Herve Catan , Vincent Gillet
发明人： Karim Djafarian , Gilbert Laurenti , Herve Catan , Vincent Gillet
IPC分类号： G06F930
CPC分类号： G06F7/764 , G06F5/01 , G06F7/607 , G06F7/74 , G06F7/762 , G06F9/30018 , G06F9/30032 , G06F9/3013 , G06F9/30134 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F9/32 , G06F9/321 , G06F9/3552 , G06F9/3822 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3867 , G06F9/3879 , G06F9/3885 , G06F9/3891
摘要： A processing engine 10 includes an instruction buffer 502 operable to buffer single and compound instructions pending execution. A decode mechanism is configured to decode instructions from the instruction buffer. The decode mechanism is arranged to respond to a predetermined tag in a tag field of an instruction, which predetermined tag is representative of the instruction being a compound instruction formed from separate programmed memory instructions. The decode mechanism is operable in response to the predetermined tag to decode at least first data flow control for a first programmed instruction and second data flow control for a second programmed instruction. The use of compound instructions enables effective use of the bandwidth available within the processing engine. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. A compound address field of the predetermined compound instruction can be arranged at the same bit positions as the address field for a hard compound memory instruction, that is a compound instruction which is programmed. In this case the decoding of the addresses can be started before the operation code of the instructions have been decoded. To reduce the number of bits in the compound instruction, addressing can be restricted to indirect addressing and the operation codes for at least the first instruction can be reduced in size. In this way, the compound instruction can be arranged to have the same number of bits in total as the sum of the bits of the separate programmed instructions.
摘要翻译：处理引擎10包括指令缓冲器502，其可操作用于在执行之前缓冲单个和复合指令。解码机构被配置为解码来自指令缓冲器的指令。解码机构被布置成响应于指令的标签字段中的预定标签，该预定标签表示作为由单独的编程存储器指令形成的复合指令的指令。解码机制可响应于预定标签而操作，以对第一编程指令和第二编程指令的第二数据流控制进行至少第一数据流控制解码。使用复合指令可以有效利用处理引擎内可用的带宽。可以从单独的第一和第二编程存储器指令编译软双存储器指令。预定复合指令的复合地址字段可以被布置在与用于硬化合物存储器指令的地址字段相同的位位置，即，被编程的复合指令。在这种情况下，可以在指令的操作代码被解码之前开始地址的解码。为了减少复合指令中的位数，可以将寻址限制为间接寻址，并且可以减小至少第一条指令的操作码的大小。以这种方式，复合指令可以被布置为具有与分离的编程指令的位的总和相同数量的位。

8. 发明授权

US06654876B1 System for rejecting and reissuing instructions after a variable delay time period 失效
标题翻译：在可变延迟时间段后拒绝和重新发出指令的系统
公开(公告)号：US06654876B1
公开(公告)日：2003-11-25
申请号：US09434875
申请日：1999-11-04
申请人： Hung Qui Le , David James Shippy
发明人： Hung Qui Le , David James Shippy
IPC分类号： G06F930
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3859 , G06F9/3865
摘要： A method, processor, and data processing system implementing a delayed reject mechanism are disclosed. The processor includes an issue unit suitable for issuing an instruction in a first cycle and a load store unit (LSU). The LSU includes an extend reject calculator circuit configured to receive a set of completion information signals and generate a delay value based thereon. The LSU is adapted to determine whether to reject the instruction in a determination cycle. The number of cycles between the first cycle and the determination cycle is a function of the delay value such that reject timing is variable with respect to the first cycle. In one embodiment, the processor is further configured to reissue the instruction after the determination cycle if the instruction was rejected in the determination cycle. The delay value is conveyed via a 2-bit bus in one embodiment. The 2 bit bus permits delaying the determination cycle from 0 to 3 cycles after a finish cycle. In one embodiment, the number of cycles between the first cycle and the determination cycle includes the number of cycles required to travel a pipeline of the microprocessor plus the number of cycles indicated by the delay value.
摘要翻译：公开了一种实现延迟拒绝机制的方法，处理器和数据处理系统。该处理器包括适于在第一周期中发出指令的发布单元和负载存储单元（LSU）。 LSU包括扩展拒绝计算器电路，被配置为接收一组完成信息信号并基于此生成延迟值。 LSU适于确定是否在确定周期中拒绝该指令。第一周期和确定周期之间的周期数是延迟值的函数，使得拒绝定时相对于第一周期是可变的。在一个实施例中，处理器还被配置为在确定周期之后重新发出指令，如果指令在确定周期中被拒绝。在一个实施例中，延迟值通过2位总线传送。 2位总线允许在完成循环后将判定周期从0到3个周期延迟。在一个实施例中，第一周期和确定周期之间的循环次数包括行进微处理器的流水线所需的循环次数加上由延迟值指示的周期数。

9. 发明授权

US06654874B1 Microcomputer systems having compressed instruction processing capability and methods of operating same 有权
标题翻译：具有压缩指令处理能力的微机系统及其操作方法
公开(公告)号：US06654874B1
公开(公告)日：2003-11-25
申请号：US09536435
申请日：2000-03-27
申请人： Yun-Tae Lee
发明人： Yun-Tae Lee
IPC分类号： G06F930
CPC分类号： G06F9/30178 , G06F9/30189
摘要： Microcomputer systems include an instruction processor therein that can process both normal length instructions and compressed instructions. The normal length instructions and the compressed instructions are provided from memory to an instruction register and then passed through decoding circuitry to a processor core. The decoding circuitry preferably comprises a demultiplexer having a data input that receives a first multi-bit instruction from the instruction register and a select input that receives a first select signal (SEL1). A compressed instruction decoder is also provided. The compressed instruction decoder has a data input electrically coupled to a first data output of the demultiplexer and a select input that receives a second select signal (SEL2). A multiplexer is also provided. The multiplexer has a first data input electrically coupled to an output of the compressed instruction decoder, a second data input electrically coupled to a second data output of the demultiplexer and a select input that receives the first select signal (SEL1). The output of the demultiplexer is electrically coupled to the processor core.
摘要翻译：微计算机系统包括其中可以处理正常长度指令和压缩指令的指令处理器。正常长度指令和压缩指令从存储器提供给指令寄存器，然后通过解码电路传递到处理器核心。解码电路优选地包括具有从指令寄存器接收第一多位指令的数据输入和接收第一选择信号（SEL1）的选择输入的解复用器。还提供了压缩指令解码器。压缩指令解码器具有电耦合到解复用器的第一数据输出的数据输入和接收第二选择信号（SEL2）的选择输入。还提供多路复用器。多路复用器具有电耦合到压缩指令解码器的输出端的第一数据输入端，电耦合到解复用器的第二数据输出端的第二数据输入端和接收第一选择信号（SEL1）的选择输入端。多路分解器的输出电耦合到处理器核心。

10. 发明授权

US06647485B2 High-performance, superscalar-based computer system with out-of-order instruction execution 失效
公开(公告)号：US06647485B2
公开(公告)日：2003-11-11
申请号：US09852293
申请日：2001-05-10
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F930
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

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