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1. 发明授权

US09632778B2 Gather/scatter of multiple data elements with packed loading/storing into /from a register file entry 有权
公开(公告)号：US09632778B2
公开(公告)日：2017-04-25
申请号：US13569363
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Embodiments relate to packed loading and storing of data. An aspect includes a system for packed loading and storing of distributed data. The system includes memory and a processing element configured to communicate with the memory. The processing element is configured to perform a method including fetching and decoding an instruction for execution by the processing element. A plurality of individually addressable data elements is gathered from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The processing element packs and loads the data elements into register file elements of a register file entry based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.

2. 发明申请

US20140040599A1 PACKED LOAD/STORE WITH GATHER/SCATTER 审中-公开
标题翻译：包装加载/存储与GATHER / SCATTER
公开(公告)号：US20140040599A1
公开(公告)日：2014-02-06
申请号：US13569363
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Embodiments relate to packed loading and storing of data. An aspect includes a system for packed loading and storing of distributed data. The system includes memory and a processing element configured to communicate with the memory. The processing element is configured to perform a method including fetching and decoding an instruction for execution by the processing element. A plurality of individually addressable data elements is gathered from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The processing element packs and loads the data elements into register file elements of a register file entry based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.
摘要翻译：实施例涉及数据的打包加载和存储。一个方面包括用于打包加载和存储分布式数据的系统。该系统包括存储器和被配置为与存储器通信的处理元件。处理元件被配置为执行一种方法，包括对由处理元件执行的指令进行取出和解码。基于该指令，多个可单独寻址的数据元素从存储器中的不连续位置收集，该位置比处理元件中的寄存器文件元素的标称宽度窄。处理元件基于指令将数据元素打包并加载到寄存器文件条目的寄存器文件元素中，使得从存储器中的非连续位置收集的至少两个数据元素被打包并加载到单个寄存器注册文件条目的文件元素。

3. 发明申请

US20140040596A1 PACKED LOAD/STORE WITH GATHER/SCATTER 有权
标题翻译：包装加载/存储与GATHER / SCATTER
公开(公告)号：US20140040596A1
公开(公告)日：2014-02-06
申请号：US13566141
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Embodiments relate to packed loading and storing of data. An aspect includes a method for packed loading and storing of data distributed in a system that includes memory and a processing element. The method includes fetching and decoding an instruction for execution by the processing element. The processing element gathers a plurality of individually addressable data elements from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The data elements are packed and loaded into register file elements of a register file entry by the processing element based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.
摘要翻译：实施例涉及数据的打包加载和存储。一方面包括一种用于打包加载和存储分布在包括存储器和处理元件的系统中的数据的方法。该方法包括获取和解码由处理元件执行的指令。处理元件从存储器中的非连续位置收集多个可单独寻址的数据元素，该数据元素比基于指令的处理元件中的寄存器文件元素的标称宽度更窄。所述数据元素根据所述指令由所述处理元件打包并加载到寄存器文件条目的寄存器文件元素中，使得从存储器中的非连续位置收集的至少两个数据元素被打包并加载到注册文件条目的单个注册文件元素。

4. 发明授权

US09632777B2 Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry 有权
公开(公告)号：US09632777B2
公开(公告)日：2017-04-25
申请号：US13566141
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Jaime H. Moreno , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30036
摘要： Embodiments relate to packed loading and storing of data. An aspect includes a method for packed loading and storing of data distributed in a system that includes memory and a processing element. The method includes fetching and decoding an instruction for execution by the processing element. The processing element gathers a plurality of individually addressable data elements from non-contiguous locations in the memory which are narrower than a nominal width of register file elements in the processing element based on the instruction. The data elements are packed and loaded into register file elements of a register file entry by the processing element based on the instruction, such that at least two of the data elements gathered from the non-contiguous locations in the memory are packed and loaded into a single register file element of the register file entry.

5. 发明授权

US09003160B2 Active buffered memory 有权
标题翻译：主动缓冲内存
公开(公告)号：US09003160B2
公开(公告)日：2015-04-07
申请号：US13566019
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , James A. Kahle , Jaime H. Moreno , Ravi Nair
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , James A. Kahle , Jaime H. Moreno , Ravi Nair
IPC分类号： G06F12/10 , G06F9/445
CPC分类号： G06F9/44578 , G06F12/10 , Y02D10/13
摘要： According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction loaded from a first memory location in the memory, and performing, by the processing element, the program, the performing including loading data in the processing element from a second memory location in the memory. The method also includes generating, by the processing element, a virtual address of the second memory location based on the load instruction and translating, by the processing element, the virtual address into a real address.
摘要翻译：根据本发明的一个实施例，一种用于操作包括存储器和处理元件的存储器件的方法包括在处理元件中接收来自请求器的命令，在处理元件中接收基于该命令的程序所述程序包括从所述存储器中的第一存储器位置加载的加载指令，并且由所述处理元件执行所述程序，所述执行包括来自所述存储器中的第二存储器位置的所述处理元件中的加载数据。该方法还包括由处理元件基于加载指令产生第二存储器位置的虚拟地址，并由处理元件将虚拟地址转换为实际地址。

6. 发明申请

US20140040592A1 ACTIVE BUFFERED MEMORY 有权
标题翻译：主动缓冲存储器
公开(公告)号：US20140040592A1
公开(公告)日：2014-02-06
申请号：US13566019
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , James A. Kahle , Jaime H. Moreno , Ravi Nair
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , James A. Kahle , Jaime H. Moreno , Ravi Nair
IPC分类号： G06F12/10
CPC分类号： G06F9/44578 , G06F12/10 , Y02D10/13
摘要： According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction loaded from a first memory location in the memory, and performing, by the processing element, the program, the performing including loading data in the processing element from a second memory location in the memory. The method also includes generating, by the processing element, a virtual address of the second memory location based on the load instruction and translating, by the processing element, the virtual address into a real address.
摘要翻译：根据本发明的一个实施例，一种用于操作包括存储器和处理元件的存储器件的方法包括在处理元件中接收来自请求器的命令，在处理元件中接收基于该命令的程序所述程序包括从所述存储器中的第一存储器位置加载的加载指令，并且由所述处理元件执行所述程序，所述执行包括来自所述存储器中的第二存储器位置的所述处理元件中的加载数据。该方法还包括由处理元件基于加载指令产生第二存储器位置的虚拟地址，并由处理元件将虚拟地址转换为实际地址。

7. 发明申请

US20140040598A1 VECTOR PROCESSING IN AN ACTIVE MEMORY DEVICE 审中-公开
标题翻译：主动存储器件中的矢量处理
公开(公告)号：US20140040598A1
公开(公告)日：2014-02-06
申请号：US13569359
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/30036 , G06F9/30065 , G06F9/3879 , G06F9/3887 , G06F15/8007 , G06F15/8053 , G06F15/8084
摘要： Embodiments relate to vector processing in an active memory device. An aspect includes a system for vector processing in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method including decoding an instruction with a plurality of sub-instructions to execute in parallel. An iteration count to repeat execution of the sub-instructions in parallel is determined. Execution of the sub-instructions is repeated in parallel for multiple iterations, by the processing element, based on the iteration count. Multiple locations in the memory are accessed in parallel based on the execution of the sub-instructions.
摘要翻译：实施例涉及有源存储器件中的矢量处理。一个方面包括用于有源存储器设备中的向量处理的系统。该系统包括有源存储器设备中的存储器和有源存储器设备中的处理元件。处理单元被配置为执行包括用多个子指令解码指令并行执行的方法。确定并行重复子指令执行的迭代次数。基于迭代计数，由处理元件并行地重复子指令的执行多次迭代。基于子指令的执行，并行地访问存储器中的多个位置。

8. 发明授权

US09535694B2 Vector processing in an active memory device 有权
标题翻译：有源存储设备中的向量处理
公开(公告)号：US09535694B2
公开(公告)日：2017-01-03
申请号：US13569359
申请日：2012-08-08
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Daniel A. Prener
IPC分类号： G06F15/00 , G06F1/04 , G06F9/30 , G06F9/38 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/30065 , G06F9/3879 , G06F9/3887 , G06F15/8007 , G06F15/8053 , G06F15/8084
摘要： Embodiments relate to vector processing in an active memory device. An aspect includes a system for vector processing in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method including decoding an instruction with a plurality of sub-instructions to execute in parallel. An iteration count to repeat execution of the sub-instructions in parallel is determined. Execution of the sub-instructions is repeated in parallel for multiple iterations, by the processing element, based on the iteration count. Multiple locations in the memory are accessed in parallel based on the execution of the sub-instructions.
摘要翻译：实施例涉及有源存储器件中的矢量处理。一个方面包括用于有源存储器设备中的向量处理的系统。该系统包括有源存储器设备中的存储器和有源存储器设备中的处理元件。处理单元被配置为执行包括用多个子指令解码指令并行执行的方法。确定并行重复子指令执行的迭代次数。基于迭代计数，由处理元件并行地重复子指令的执行多次迭代。基于子指令的执行，并行地访问存储器中的多个位置。

9. 发明授权

US09575755B2 Vector processing in an active memory device 有权
标题翻译：有源存储设备中的向量处理
公开(公告)号：US09575755B2
公开(公告)日：2017-02-21
申请号：US13566135
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/30 , G06F9/38 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/30065 , G06F9/3879 , G06F9/3887 , G06F15/8007 , G06F15/8053 , G06F15/8084
摘要： Embodiments relate to vector processing in an active memory device. An aspect includes a method for vector processing in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in parallel. An iteration count to repeat execution of the sub-instructions in parallel is determined. Based on the iteration count, execution of the sub-instructions in parallel is repeated for multiple iterations by the processing element. Multiple locations in the memory are accessed in parallel based on the execution of the sub-instructions.
摘要翻译：实施例涉及有源存储器件中的矢量处理。一个方面包括一种用于在包括存储器和处理元件的有源存储器件中进行向量处理的方法。该方法包括在处理元件中解码包括并行执行的多个子指令的指令。确定并行重复子指令执行的迭代次数。基于迭代计数，并行处理子指令的执行由处理元件重复进行多次迭代。基于子指令的执行，并行地访问存储器中的多个位置。

10. 发明申请

US20140040603A1 VECTOR PROCESSING IN AN ACTIVE MEMORY DEVICE 有权
标题翻译：主动存储器件中的矢量处理
公开(公告)号：US20140040603A1
公开(公告)日：2014-02-06
申请号：US13566135
申请日：2012-08-03
申请人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Daniel A. Prener
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair , Daniel A. Prener
IPC分类号： G06F9/302 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/30065 , G06F9/3879 , G06F9/3887 , G06F15/8007 , G06F15/8053 , G06F15/8084
摘要： Embodiments relate to vector processing in an active memory device. An aspect includes a method for vector processing in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in parallel. An iteration count to repeat execution of the sub-instructions in parallel is determined. Based on the iteration count, execution of the sub-instructions in parallel is repeated for multiple iterations by the processing element. Multiple locations in the memory are accessed in parallel based on the execution of the sub-instructions.
摘要翻译：实施例涉及有源存储器件中的矢量处理。一个方面包括一种用于在包括存储器和处理元件的有源存储器件中进行向量处理的方法。该方法包括在处理元件中解码包括并行执行的多个子指令的指令。确定并行重复子指令执行的迭代次数。基于迭代计数，并行处理子指令的执行由处理元件重复进行多次迭代。基于子指令的执行，并行地访问存储器中的多个位置。

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