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1. 发明申请

US20110318898A1 HARD MASK FOR THIN FILM RESISTOR MANUFACTURE 有权
标题翻译：薄膜电阻器制造的硬掩模
公开(公告)号：US20110318898A1
公开(公告)日：2011-12-29
申请号：US12824495
申请日：2010-06-28
申请人： Li-Wen Chang , Der-Chyang Yeh , Chung-Yi Yu , Hsun-Chung Kuang , Hua-Chou Tseng , Chih-Ping Chao , Ming Chyi Liu , Yuan-Tai Tseng
发明人： Li-Wen Chang , Der-Chyang Yeh , Chung-Yi Yu , Hsun-Chung Kuang , Hua-Chou Tseng , Chih-Ping Chao , Ming Chyi Liu , Yuan-Tai Tseng
IPC分类号： H01L21/02
CPC分类号： H01L28/20 , H01L28/24
摘要： Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer.
摘要翻译：公开了制造诸如薄膜电阻器的集成电路器件的方法。一种示例性方法包括提供半导体衬底; 在所述半导体衬底上形成电阻层; 在所述电阻层上形成硬掩模层，其中所述硬掩模层包括所述电阻层上的阻挡层和所述阻挡层上的电介质层; 以及在所述硬掩模层中形成暴露所述电阻层的一部分的开口。

2. 发明授权

US07705428B2 Varactor 有权
公开(公告)号：US07705428B2
公开(公告)日：2010-04-27
申请号：US11386363
申请日：2006-03-21
申请人： Cheng-Chou Hung , Hua-Chou Tseng
发明人： Cheng-Chou Hung , Hua-Chou Tseng
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L29/94
摘要： A varactor on a substrate is provided. The varactor comprises a bottom electrode, an upper electrode, a first dielectric layer and a conductive layer. The bottom electrode has several doped regions arranged in the substrate as an array with several rows and several columns, wherein the doped regions in adjacent columns are arranged alternatively. The upper electrode is located over the substrate and the upper electrode is composed of several electrode locations and has several openings, wherein each opening exposes the corresponding doped region. Furthermore, each electrode location is surrounded by three doped regions. The first dielectric layer is located between the substrate and the upper electrode. The conductive layer is located over the upper electrode, wherein the conductive layer and the upper electrode are isolated from each other and the conductive layer and the doped regions are electrically connected to each other.
摘要翻译：提供了基板上的变容二极管。变容二极管包括底电极，上电极，第一电介质层和导电层。底部电极具有布置在衬底中的几个掺杂区域作为具有几行和几列的阵列，其中相邻列中的掺杂区域交替排列。上电极位于衬底上方，上电极由几个电极位置组成并且具有若干个开口，其中每个开口暴露相应的掺杂区域。此外，每个电极位置被三个掺杂区围绕。第一电介质层位于衬底和上电极之间。导电层位于上电极之上，其中导电层和上电极彼此隔离，并且导电层和掺杂区彼此电连接。

3. 发明授权

US07321285B2 Method for fabricating a transformer integrated with a semiconductor structure 有权
公开(公告)号：US07321285B2
公开(公告)日：2008-01-22
申请号：US11736565
申请日：2007-04-17
申请人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
发明人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.

4. 发明申请

US20080012092A1 STRUCTURE OF CAPACITOR SET AND METHOD FOR REDUCING CAPACITANCE VARIATION BETWEEN CAPACITORS 有权
标题翻译：电容器结构和减少电容之间电容变化的方法
公开(公告)号：US20080012092A1
公开(公告)日：2008-01-17
申请号：US11309164
申请日：2006-07-04
申请人： Victor-Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
发明人： Victor-Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
IPC分类号： H01L29/00
CPC分类号： H01L28/91 , H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.
摘要翻译：描述了电容器组的结构，其包括设置在基板上的相同位置处的至少两个电容器，并且包括第一电容器和第二电容器。第一电容器包括并联电连接的多个第一电容器单元。第二电容器包括并联电连接的多个第二电容器单元。第一和第二电容器单元彼此空间上相互混合以形成阵列。

5. 发明申请

US20070236320A1 METHOD FOR FABRICATING A TRANSFORMER INTEGRATED WITH A SEMICONDUCTOR STRUCTURE 有权
标题翻译：一种用半导体结构集成的变压器的方法
公开(公告)号：US20070236320A1
公开(公告)日：2007-10-11
申请号：US11736565
申请日：2007-04-17
申请人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
发明人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.
摘要翻译：提供基板，并在其上形成顶部互连金属层和初级绕组层。然后在基板上形成具有顶部互连金属层的多个通孔露出部分的钝化层。在钝化层上形成次级绕组层和至少一个焊盘。接合焊盘通过通孔电连接到顶部互连金属层。

6. 发明授权

US07271428B2 Heterojunction bipolar transistor 有权
标题翻译：异质结双极晶体管
公开(公告)号：US07271428B2
公开(公告)日：2007-09-18
申请号：US11021246
申请日：2004-12-21
申请人： Cheng-Wen Fan , Hua-Chou Tseng
发明人： Cheng-Wen Fan , Hua-Chou Tseng
IPC分类号： H01L31/0328
CPC分类号： H01L29/66242 , H01L29/66318
摘要： The invention provides a heterojunction bipolar transistor comprising a substrate having a collector therein, an intrinsic base region, a first extrinsic base region, a second extrinsic base region, an emitter on the intrinsic base layer and a spacer adjacent the emitter and on the first extrinsic base region. The first extrinsic base region is adjacent the intrinsic base region and the second extrinsic base region is adjacent the first extrinsic base region on the substrate, wherein a dopant concentration of the second extrinsic base region is higher than a dopant concentration of the first extrinsic base region.
摘要翻译：本发明提供了一种异质结双极晶体管，其包括其中具有集电极的衬底，本征基极区域，第一非本征基极区域，第二非本征基极区域，本征基极层上的发射极和邻近发射极的间隔区以及与第一外部基极基地区。第一非本征基区与本征基区相邻，第二非本征基区与衬底上的第一非本征基区邻接，其中第二非本征基区的掺杂浓度高于第一非本征基区的掺杂浓度。

7. 发明授权

US06855611B2 Fabrication method of an electrostatic discharge protection circuit with a low resistant current path 有权
标题翻译：具有低电阻电流路径的静电放电保护电路的制造方法
公开(公告)号：US06855611B2
公开(公告)日：2005-02-15
申请号：US10259947
申请日：2002-09-30
申请人： Shiao-Shien Chen , Tsun-Lai Hsu , Tien-Hao Tang , Hua-Chou Tseng
发明人： Shiao-Shien Chen , Tsun-Lai Hsu , Tien-Hao Tang , Hua-Chou Tseng
IPC分类号： H01L21/331 , H01L21/8238 , H01L21/8249 , H01L23/60 , H01L23/62 , H01L27/02 , H01L27/06 , H01L27/092
CPC分类号： H01L27/0266 , H01L21/823814 , H01L21/8249 , H01L27/0623 , H01L27/0922
摘要： A fabrication method of an electrostatic discharge protection circuit is described, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.
摘要翻译：描述了静电放电保护电路的制造方法，其中在静电放电保护电路的衬底中形成掩埋层，并且还在其中形成与埋层电连接的沉降片和漏极。因此，当静电放电保护电路被激活时，电流从源极通过掩埋层和沉降片流向漏极。电流流动路径远离栅介质层，以避免大电流损坏栅极电介质，从而提高静电放电保护电路的绝缘强度。

8. 发明授权

US06559016B2 Method of manufacturing low-leakage, high-performance device 有权
公开(公告)号：US06559016B2
公开(公告)日：2003-05-06
申请号：US09733822
申请日：2000-12-05
申请人： Hua-Chou Tseng , Tony Lin
发明人： Hua-Chou Tseng , Tony Lin
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26586 , H01L29/1083 , H01L29/6656 , H01L29/7833
摘要： A method of manufacturing a low-leakage, high-performance device. A substrate having a gate electrode thereon is provided. A lightly doped, high-energy implantation is conducted to form a lightly doped source/drain terminal in the substrate. An offset spacer is formed on each sidewall of the gate electrode. A heavily doped implantation is conducted to form a heavily doped source/drain terminal in the substrate. The heavily doped source/drain terminal has a depth smaller than the lightly doped source/drain terminal. A protective spacer structure is formed on each sidewall of the gate electrode. A deep-penetration source/drain implantation is carried out to form a deep source/drain terminal in the substrate.

9. 发明授权

US06190982B1 Method of fabricating a MOS transistor on a semiconductor wafer 有权
标题翻译：在半导体晶片上制造MOS晶体管的方法
公开(公告)号：US06190982B1
公开(公告)日：2001-02-20
申请号：US09492670
申请日：2000-01-28
申请人： Hua-Chou Tseng , Chien-Ting Lin
发明人： Hua-Chou Tseng , Chien-Ting Lin
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/28247 , H01L29/665
摘要： The present invention relates to a method of fabricating a MOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate. A gate is first formed in a predetermined area on the surface of the semiconductor wafer. A first ion implantation process is then performed to form a doped area on the surface of the silicon substrate adjacent to the gate, the doped area serving as a heavily doped drain (HDD). A uniform and oxygen-free dielectric layer is formed on the surface of the semiconductor wafer that covers the gate. A spacer is formed on each wall of the gate. Finally, a second ion implantation process is performed to form a source and a drain on the surface of the silicon substrate adjacent to the spacer.
摘要翻译：本发明涉及在半导体晶片上制造MOS晶体管的方法。半导体晶片包括硅衬底。首先在半导体晶片的表面上的预定区域中形成栅极。然后执行第一离子注入工艺以在硅衬底的与栅极相邻的表面上形成掺杂区域，掺杂区域用作重掺杂漏极（HDD）。在覆盖栅极的半导体晶片的表面上形成均匀的无氧介电层。在门的每个壁上形成间隔物。最后，进行第二离子注入工艺以在硅衬底的与间隔物相邻的表面上形成源极和漏极。

10. 发明授权

US09620421B2 Metal gate transistor, integrated circuits, systems, and fabrication methods thereof 有权
公开(公告)号：US09620421B2
公开(公告)日：2017-04-11
申请号：US12948184
申请日：2010-11-17
申请人： Chien-Chih Ho , Chih-Ping Chao , Hua-Chou Tseng , Chun-Hung Chen , Chia-Yi Su , Alex Kalnitsky , Jye-Yen Cheng , Harry-Hak-Lay Chuang
发明人： Chien-Chih Ho , Chih-Ping Chao , Hua-Chou Tseng , Chun-Hung Chen , Chia-Yi Su , Alex Kalnitsky , Jye-Yen Cheng , Harry-Hak-Lay Chuang
IPC分类号： H01L21/8238 , H01L21/768 , H01L21/8234 , H01L29/51 , H01L29/66
CPC分类号： H01L23/481 , H01L21/76802 , H01L21/76816 , H01L21/76895 , H01L21/823425 , H01L21/823475 , H01L21/823842 , H01L21/823871 , H01L27/088 , H01L29/0653 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.

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