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1. 发明授权

US07372168B2 Semiconductor chip capable of implementing wire bonding over active circuits 有权
标题翻译：能够在有源电路上实现引线键合的半导体芯片
公开(公告)号：US07372168B2
公开(公告)日：2008-05-13
申请号：US11379572
申请日：2006-04-21
申请人： Bing-Chang Wu , Kun-Chih Wang , Mei-Ling Chao , Shiao-Shien Chen
发明人： Bing-Chang Wu , Kun-Chih Wang , Mei-Ling Chao , Shiao-Shien Chen
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L23/53228 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/05042 , H01L2924/13091 , H01L2924/14 , H01L2924/00014
摘要： A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor substrate.
摘要翻译：提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。该半导体芯片包括一个焊盘结构，该焊盘结构包括一个可粘合的金属焊盘，一个顶部互连金属层，一个应力缓冲电介质，以及至少一个可焊接的金属焊盘和顶部互连金属层之间的第一通孔塞。半导体芯片还至少包括互连金属层，在互连金属层和焊盘结构之间的至少第二通孔插塞以及位于半导体衬底上的焊盘结构下方的有源电路。

2. 发明授权

US07233475B1 Integrated circuit with an electrostatic discharge protection circuit 有权
标题翻译：具有静电放电保护电路的集成电路
公开(公告)号：US07233475B1
公开(公告)日：2007-06-19
申请号：US11279572
申请日：2006-04-13
申请人： Shiao-Shien Chen
发明人： Shiao-Shien Chen
IPC分类号： H02H3/22
CPC分类号： H01L27/0266
摘要： MOS Transistors and bipolar junction transistors are connected to input pads and output pads for implementing electrostatic discharge protection. By conducting a power clamp circuit and applying a substrate-trigger technology, electrostatic discharge protection is further enhanced. For instance, positive ESD stress protection can be enhanced between signal pads (input pads and output pads) and VSS by using NMOS transistors and field oxide devices. Negative ESD stress protection can be enhanced between signal pads and VDD by using PMOS transistors.
摘要翻译： MOS晶体管和双极结晶体管连接到用于实现静电放电保护的输入焊盘和输出焊盘。通过进行功率钳位电路和施加衬底触发技术，进一步增强了静电放电保护。例如，通过使用NMOS晶体管和场氧化物器件，可以在信号焊盘（输入焊盘和输出焊盘）和VSS之间增强正的ESD应力保护。通过使用PMOS晶体管，可以在信号焊盘和VDD之间增强负ESD保护。

3. 发明申请

US20050242416A1 LOW-CAPACITANCE BONDING PAD FOR SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于半导体器件的低电容贴片
公开(公告)号：US20050242416A1
公开(公告)日：2005-11-03
申请号：US10709366
申请日：2004-04-29
申请人： Shiao-Shien Chen
发明人： Shiao-Shien Chen
IPC分类号： H01L23/485 , H01L23/522 , H01L23/62
CPC分类号： H01L24/05 , H01L23/5222 , H01L2224/02166 , H01L2224/05093 , H01L2224/05556 , H01L2924/00014 , H01L2924/01005 , H01L2924/01015 , H01L2924/01033 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： A low capacitance semiconductor device is provided. The low capacitance semiconductor device comprises a triple well structure in the substrate, and a bonding pad structure on the substrate, wherein the substrate having a doped region of a second conductive type, a first well region of first conductive type, and a second well region of second conductive type. There is a first junction capacitance between the diffusion region and the first well region, a second junction capacitance between the first well region and the second well region, and a third capacitance between the second well region and the substrate. The first junction capacitance, second junction capacitance, the third junction capacitance and the total equivalent capacitance are coupled in series, such that the total parasitic capacitance is effectively reduced.
摘要翻译：提供了一种低电容半导体器件。低电容半导体器件包括衬底中的三阱结构和衬底上的焊盘结构，其中衬底具有第二导电类型的掺杂区域，第一导电类型的第一阱区域和第二阱区域的第二导电类型。扩散区和第一阱区之间存在第一结电容，第一阱区和第二阱区之间的第二结电容以及第二阱区和衬底之间的第三电容。第一结电容，第二结电容，第三结电容和总等效电容串联耦合，从而有效减少总寄生电容。

4. 发明授权

US06479883B1 Electrostatic discharge protection circuit 失效
标题翻译：静电放电保护电路
公开(公告)号：US06479883B1
公开(公告)日：2002-11-12
申请号：US09585563
申请日：2000-06-02
申请人： Shiao-Shien Chen , Tien-Hao Tang
发明人： Shiao-Shien Chen , Tien-Hao Tang
IPC分类号： H01L2900
CPC分类号： H01L27/0266 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection circuit formed between an input/output pad and an internal circuit that can be applied to a silicon-on-insulator type of MOSFET. The protection circuit includes two n-type tunneling source-body contact devices connected in a series to form two sets of parasitic diode/zener diode pairs that serve as electrostatic discharge routes. When an excessive positive voltage or negative voltage is applied, one of the n-type tunneling source-body contact devices becomes a conductive NMOS transistor forming a discharge route for electrostatic charges. Meanwhile, the other n-type device operates reversely and acts like a zener diode when a definite voltage is exceeded. The zener diode, together with a parasitic diode, provides another discharge route for electrostatic charges.
摘要翻译：在输入/输出焊盘和内部电路之间形成的静电放电保护电路，可以应用于绝缘体上硅的MOSFET上。保护电路包括串联连接的两个n型隧道源体接触装置，以形成用作静电放电路径的两组寄生二极管/齐纳二极管对。当施加过大的正电压或负电压时，n型隧道源体接触装置中的一个成为形成静电电荷放电路径的导电NMOS晶体管。同时，当超过一定电压时，另一个n型器件反向工作，并且像齐纳二极管一样工作。齐纳二极管与寄生二极管一起为静电充电提供了另一种放电路径。

5. 发明授权

US07719813B2 Gate-coupled substrate-triggered ESD protection circuit and integrated circuit therewith 有权
标题翻译：栅极耦合衬底触发ESD保护电路及其集成电路
公开(公告)号：US07719813B2
公开(公告)日：2010-05-18
申请号：US11163466
申请日：2005-10-20
申请人： Shiao-Shien Chen
发明人： Shiao-Shien Chen
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： An ESD protection design using a gate-coupled substrate-triggered technique is provided. A required RC time constant maintained in the gate-coupled substrate-triggered ESD circuit is based on a parasitic MOS capacitor and larger resistor, in which a layout area for the substrate-triggered ESD protection design is significantly reduced.
摘要翻译：提供使用栅极耦合衬底触发技术的ESD保护设计。栅极耦合衬底触发ESD电路中保持的所需RC时间常数基于寄生MOS电容器和较大电阻器，其中用于衬底触发的ESD保护设计的布局面积显着减小。

6. 发明授权

US07176539B2 Layout of semiconductor device with substrate-triggered ESD protection 有权
标题翻译：具有基板触发ESD保护的半导体器件布局
公开(公告)号：US07176539B2
公开(公告)日：2007-02-13
申请号：US10904214
申请日：2004-10-29
申请人： Shiao-Shien Chen
发明人： Shiao-Shien Chen
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/0207 , H01L27/0266
摘要： A semiconductor device with substrate-triggered ESD protection has a guard ring, a first MOS transistor array, a second MOS transistor array, a substrate-triggered portion, and an N-well. The first MOS transistor array, the second MOS transistor array, the substrate-triggered portion, and the N-well are formed in a region surrounded by the guard ring, and the substrate-triggered portion is located between the first MOS transistor array and the second MOS transistor array. When the ESD event occurs, the N-well is biased for directing a trigger current.
摘要翻译：具有衬底触发ESD保护的半导体器件具有保护环，第一MOS晶体管阵列，第二MOS晶体管阵列，衬底触发部分和N阱。第一MOS晶体管阵列，第二MOS晶体管阵列，基板触发部分和N阱形成在由保护环包围的区域中，并且基板触发部分位于第一MOS晶体管阵列和第一MOS晶体管阵列之间第二MOS晶体管阵列。当ESD事件发生时，N阱被偏置以引导触发电流。

7. 发明授权

US07068482B2 BiCMOS electrostatic discharge power clamp 失效
标题翻译： BiCMOS静电放电电源钳
公开(公告)号：US07068482B2
公开(公告)日：2006-06-27
申请号：US10387555
申请日：2003-03-14
申请人： Shiao-Shien Chen
发明人： Shiao-Shien Chen
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： A BiCMOS electrostatic discharge (ESD) protecting circuit is triggered by a bipolar junction transistor (BJT) for achieving ESD protection. Due to the layout area of the BJT ESD protecting circuit being smaller than the layout area of an RC circuit, layout area can be reduced. Moreover, the BJT reduces leakage current problems and has a lower triggering voltage. Therefore, the BJT in the ESD protecting circuit can effectively reduce problems of a higher triggering ESD voltage and leakage current.
摘要翻译： BiCMOS静电放电（ESD）保护电路由用于实现ESD保护的双极结型晶体管（BJT）触发。由于BJT ESD保护电路的布局面积小于RC电路的布局面积，可以减小布局面积。此外，BJT减少漏电流问题，并具有较低的触发电压。因此，ESD保护电路中的BJT可以有效降低触发ESD电压和漏电流的问题。

8. 发明申请

US20060027871A1 [ELECTROSTATIC DISCHARGE PROTECTION DEVICE] 审中-公开
标题翻译： [静电放电保护装置]
公开(公告)号：US20060027871A1
公开(公告)日：2006-02-09
申请号：US10710818
申请日：2004-08-05
申请人： Shiao-Shien Chen
发明人： Shiao-Shien Chen
IPC分类号： H01L23/62
CPC分类号： H01L27/0255
摘要： An electrostatic discharge (ESD) protection device including an ESD protection circuit is provided. The ESD protection circuit includes at least a diode connected in series between a first voltage and a pad, and at least an ESD component connected in series between a second voltage and a pad. Each of the at least an ESD component comprises a deep N-well region formed in a P-type substrate, a triple P-well formed in the deep N-well region, and a highly doped N-type (N+) region and a highly doped P-type (P+) region formed in the triple P-well region.
摘要翻译：提供了包括ESD保护电路的静电放电（ESD）保护装置。 ESD保护电路至少包括串联连接在第一电压和焊盘之间的二极管以及至少连接在第二电压和焊盘之间的ESD部件。所述至少一个ESD部件中的每一个包括在P型衬底中形成的深N阱区，在深N阱区中形成的三重P阱以及高掺杂N型（N +）区和在三重P阱区域中形成的高掺杂P型（P +）区。

9. 发明申请

US20060023379A1 [ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND CIRCUIT THEREOF] 有权
标题翻译： [静电放电保护装置及其电路]
公开(公告)号：US20060023379A1
公开(公告)日：2006-02-02
申请号：US10710695
申请日：2004-07-29
申请人： Shiao-Shien Chen
发明人： Shiao-Shien Chen
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An electrostatic discharge (ESD) protection circuit including a detection circuit for detecting the ESD current and a clamp circuit for bypassing an ESD current between a first pad and a second pad is provided. The detection circuit is connected between the first pad and the second pad, wherein the detection circuit comprises a diode and a variable resistor tuned by a diode, and an output terminal of the detection circuit is connected to the variable resistor. The clamp circuit is connected between the first pad and the second pad and connected to the output terminal of the detection circuit. When the ESD current from the first pad or the second pad is detected by the detection circuit, a trigger voltage is generated to trigger the clamp circuit to bypass the ESD current due to a resistance of the variable resistor is changed by the diode.
摘要翻译：提供一种静电放电（ESD）保护电路，其包括用于检测ESD电流的检测电路和用于绕过第一焊盘和第二焊盘之间的ESD电流的钳位电路。检测电路连接在第一焊盘和第二焊盘之间，其中检测电路包括二极管和由二极管调谐的可变电阻器，检测电路的输出端连接到可变电阻器。钳位电路连接在第一焊盘和第二焊盘之间，并连接到检测电路的输出端。当由检测电路检测到来自第一焊盘或第二焊盘的ESD电流时，由于二极管改变可变电阻器的电阻，产生触发电压以触发钳位电路旁路ESD电流。

10. 发明申请

US20060022272A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND CIRCUIT THEREOF 有权
标题翻译：静电放电保护装置及其电路
公开(公告)号：US20060022272A1
公开(公告)日：2006-02-02
申请号：US10904823
申请日：2004-12-01
申请人： Shiao-Shien Chen
发明人： Shiao-Shien Chen
IPC分类号： H01L23/62
CPC分类号： H01L27/0266
摘要： An electrostatic discharge (ESD) protection circuit including a detection circuit for detecting the ESD current and a clamp circuit for bypassing an ESD current between a first pad and a second pad is provided. The detection circuit is connected between the first pad and the second pad, wherein the detection circuit comprises a diode and a variable resistor tuned by a diode, and an output terminal of the detection circuit is connected to the variable resistor. The clamp circuit is connected between the first pad and the second pad and connected to the output terminal of the detection circuit. When the ESD current from the first pad or the second pad is detected by the detection circuit, a trigger voltage is generated to trigger the clamp circuit to bypass the ESD current due to a resistance of the variable resistor is changed by the diode.
摘要翻译：提供一种静电放电（ESD）保护电路，其包括用于检测ESD电流的检测电路和用于绕过第一焊盘和第二焊盘之间的ESD电流的钳位电路。检测电路连接在第一焊盘和第二焊盘之间，其中检测电路包括二极管和由二极管调谐的可变电阻器，检测电路的输出端连接到可变电阻器。钳位电路连接在第一焊盘和第二焊盘之间，并连接到检测电路的输出端。当由检测电路检测到来自第一焊盘或第二焊盘的ESD电流时，由于二极管改变可变电阻器的电阻，产生触发电压以触发钳位电路旁路ESD电流。

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