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1. 发明授权

US07367113B2 Method for fabricating a transformer integrated with a semiconductor structure 有权
标题翻译：用于制造与半导体结构集成的变压器的方法
公开(公告)号：US07367113B2
公开(公告)日：2008-05-06
申请号：US11278952
申请日：2006-04-06
申请人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
发明人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
IPC分类号： H01F41/02
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.
摘要翻译：提供基板，并在其上形成顶部互连金属层和初级绕组层。然后在基板上形成具有顶部互连金属层的多个通孔露出部分的钝化层。在钝化层上形成次级绕组层和至少一个焊盘。接合焊盘通过通孔电连接到顶部互连金属层。

2. 发明授权

US07705428B2 Varactor 有权
公开(公告)号：US07705428B2
公开(公告)日：2010-04-27
申请号：US11386363
申请日：2006-03-21
申请人： Cheng-Chou Hung , Hua-Chou Tseng
发明人： Cheng-Chou Hung , Hua-Chou Tseng
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L29/94
摘要： A varactor on a substrate is provided. The varactor comprises a bottom electrode, an upper electrode, a first dielectric layer and a conductive layer. The bottom electrode has several doped regions arranged in the substrate as an array with several rows and several columns, wherein the doped regions in adjacent columns are arranged alternatively. The upper electrode is located over the substrate and the upper electrode is composed of several electrode locations and has several openings, wherein each opening exposes the corresponding doped region. Furthermore, each electrode location is surrounded by three doped regions. The first dielectric layer is located between the substrate and the upper electrode. The conductive layer is located over the upper electrode, wherein the conductive layer and the upper electrode are isolated from each other and the conductive layer and the doped regions are electrically connected to each other.
摘要翻译：提供了基板上的变容二极管。变容二极管包括底电极，上电极，第一电介质层和导电层。底部电极具有布置在衬底中的几个掺杂区域作为具有几行和几列的阵列，其中相邻列中的掺杂区域交替排列。上电极位于衬底上方，上电极由几个电极位置组成并且具有若干个开口，其中每个开口暴露相应的掺杂区域。此外，每个电极位置被三个掺杂区围绕。第一电介质层位于衬底和上电极之间。导电层位于上电极之上，其中导电层和上电极彼此隔离，并且导电层和掺杂区彼此电连接。

3. 发明授权

US07321285B2 Method for fabricating a transformer integrated with a semiconductor structure 有权
公开(公告)号：US07321285B2
公开(公告)日：2008-01-22
申请号：US11736565
申请日：2007-04-17
申请人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
发明人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.

4. 发明申请

US20070236320A1 METHOD FOR FABRICATING A TRANSFORMER INTEGRATED WITH A SEMICONDUCTOR STRUCTURE 有权
标题翻译：一种用半导体结构集成的变压器的方法
公开(公告)号：US20070236320A1
公开(公告)日：2007-10-11
申请号：US11736565
申请日：2007-04-17
申请人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
发明人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.
摘要翻译：提供基板，并在其上形成顶部互连金属层和初级绕组层。然后在基板上形成具有顶部互连金属层的多个通孔露出部分的钝化层。在钝化层上形成次级绕组层和至少一个焊盘。接合焊盘通过通孔电连接到顶部互连金属层。

5. 发明申请

US20080029854A1 CONDUCTIVE SHIELDING PATTERN AND SEMICONDUCTOR STRUCTURE WITH INDUCTOR DEVICE 审中-公开
标题翻译：导电屏蔽图案和具有电感器器件的半导体结构
公开(公告)号：US20080029854A1
公开(公告)日：2008-02-07
申请号：US11462269
申请日：2006-08-03
申请人： Cheng-Chou Hung , Hua-Chou Tseng , Yu-Chia Chen , Victor-Chiang Liang , Cheng-Wen Fan
发明人： Cheng-Chou Hung , Hua-Chou Tseng , Yu-Chia Chen , Victor-Chiang Liang , Cheng-Wen Fan
IPC分类号： H01L23/552
CPC分类号： H01L23/5227 , H01L23/5225 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： The invention is directed to a conductive shielding pattern for shielding a inductor device. The conductive shielding pattern comprises a plurality of conductive layers and a plurality of diffusion regions. The conductive layers are located on a substrate. The diffusion regions are located in the substrate and the conductive layers and the diffusion regions are arranged alternatively and are free ends respectively.
摘要翻译：本发明涉及用于屏蔽电感器件的导电屏蔽图案。导电屏蔽图案包括多个导电层和多个扩散区域。导电层位于基底上。扩散区域位于衬底中，并且导电层和扩散区域交替排列并分别是自由端。

6. 发明申请

US20070234554A1 METHOD FOR FABRICATING A TRANSFORMER INTEGRATED WITH A SEMICONDUCTOR STRUCTURE 有权
公开(公告)号：US20070234554A1
公开(公告)日：2007-10-11
申请号：US11278952
申请日：2006-04-06
申请人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
发明人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
IPC分类号： H01F7/06
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.

7. 发明申请

US20070246801A1 Varactor 有权
公开(公告)号：US20070246801A1
公开(公告)日：2007-10-25
申请号：US11386363
申请日：2006-03-21
申请人： Cheng-Chou Hung , Hua-Chou Tseng
发明人： Cheng-Chou Hung , Hua-Chou Tseng
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L29/94
摘要： A varactor on a substrate is provided. The varactor comprises a bottom electrode, an upper electrode, a first dielectric layer and a conductive layer. The bottom electrode has several doped regions arranged in the substrate as an array with several rows and several columns, wherein the doped regions in adjacent columns are arranged alternatively. The upper electrode is located over the substrate and the upper electrode is composed of several electrode locations and has several openings, wherein each opening exposes the corresponding doped region. Furthermore, each electrode location is surrounded by three doped regions. The first dielectric layer is located between the substrate and the upper electrode. The conductive layer is located over the upper electrode, wherein the conductive layer and the upper electrode are isolated from each other and the conductive layer and the doped regions are electrically connected to each other.
摘要翻译：提供了基板上的变容二极管。变容二极管包括底电极，上电极，第一电介质层和导电层。底部电极具有布置在衬底中的几个掺杂区域作为具有几行和几列的阵列，其中相邻列中的掺杂区域交替排列。上电极位于衬底上方，上电极由几个电极位置组成并且具有若干个开口，其中每个开口暴露相应的掺杂区域。此外，每个电极位置被三个掺杂区围绕。第一电介质层位于衬底和上电极之间。导电层位于上电极之上，其中导电层和上电极彼此隔离，并且导电层和掺杂区彼此电连接。

8. 发明申请

US20070210402A1 Varactor 审中-公开
公开(公告)号：US20070210402A1
公开(公告)日：2007-09-13
申请号：US11370965
申请日：2006-03-07
申请人： Yu-Chia Chen , Hua-Chou Tseng , Cheng-Chou Hung
发明人： Yu-Chia Chen , Hua-Chou Tseng , Cheng-Chou Hung
IPC分类号： H01L29/93
CPC分类号： H01L29/93 , H01L29/94
摘要： A varactor including a substrate, a P well disposed in the substrate, a gate structure disposed over the substrate, a p+ source disposed in the substrate at one side of the gate structure, a p+ drain disposed in the substrate at the other side of the gate structure, and a deep N well disposed in the substrate under the P well is provided. The gate oxide of the varactor is thicker so as to reduce the probability of the current leakage occurrence.
摘要翻译：一种变容二极管，包括衬底，设置在衬底中的P阱，设置在衬底上的栅极结构，设置在栅极结构的一侧的衬底中的p +源极，设置在衬底的另一侧的p +漏极栅极结构，并且设置在P阱下的衬底中的深N阱。变容二极管的栅极氧化物较厚，从而降低电流泄漏发生的可能性。

9. 发明申请

US20070181973A1 CAPACITOR STRUCTURE 审中-公开
标题翻译：电容结构
公开(公告)号：US20070181973A1
公开(公告)日：2007-08-09
申请号：US11307396
申请日：2006-02-06
申请人： Cheng-Chou Hung , Victor Liang , Hua-Chou Tseng , Chih-Yu Tseng
发明人： Cheng-Chou Hung , Victor Liang , Hua-Chou Tseng , Chih-Yu Tseng
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure including a plurality of conductive layers, a dielectric layer and a plurality of contacts is disclosed. The conductive layers are stacked, and each conductive layer has a first conductive pattern and a second conductive pattern. The dielectric layer is disposed between the first conductive pattern and the second conductive pattern and between two adjacent conductive layers. The contacts are disposed in the dielectric layer, and electrically connected to the first conductive patterns in two adjacent conductive layers and electrically connected to the second conductive patterns in two adjacent conductive layers. Wherein, the contact electrically connecting to the first conductive patterns in two adjacent conducive layers is a first strip contact, which extends between the first conductive patterns in two adjacent conductive layers, and the boundary of the first strip contact is located within the boundary of the first conductive pattern.
摘要翻译：公开了一种包括多个导电层，电介质层和多个触点的电容器结构。导电层被堆叠，并且每个导电层具有第一导电图案和第二导电图案。电介质层设置在第一导电图案和第二导电图案之间以及两个相邻的导电层之间。触点设置在电介质层中，并且电连接到两个相邻导电层中的第一导电图案并且电连接到两个相邻导电层中的第二导电图案。其中，电连接到两个相邻导电层中的第一导电图案的触点是在两个相邻的导电层中在第一导电图案之间延伸的第一条形接触，并且第一条带接触的边界位于第一导电图案。

10. 发明授权

US08581347B2 Forming bipolar transistor through fast EPI-growth on polysilicon 有权
标题翻译：通过在多晶硅上快速EPI生长形成双极晶体管
公开(公告)号：US08581347B2
公开(公告)日：2013-11-12
申请号：US12841275
申请日：2010-07-22
申请人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
发明人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
IPC分类号： H01L29/66
CPC分类号： H01L21/8249 , H01L21/8228 , H01L27/0623 , H01L27/0826
摘要： Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well.
摘要翻译：提供了一种半导体器件，其包括形成在同一衬底上的第一晶体管和第二晶体管。第一晶体管包括第一集电极，第一基极和第一发射极。第一集电器包括设置在衬底中的第一掺杂阱。第一基底包括设置在衬底上方和第一掺杂阱上方的第一掺杂层。第一发射器包括设置在第一掺杂层的一部分上的掺杂元件。第二晶体管包括第二集电极，第二基极和第二发射极。第二集电体包括衬底的掺杂部分。第二基底包括设置在衬底中并在衬底的掺杂部分上方的第二掺杂阱。第二发射器包括设置在衬底上方和第二掺杂阱上方的第二掺杂层。

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