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1. 发明申请

US20050045956A1 Structure and fabrication method of electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路的结构与制造方法
公开(公告)号：US20050045956A1
公开(公告)日：2005-03-03
申请号：US10951373
申请日：2004-09-28
申请人： Shiao-Shien Chen , Tsun-Lai Hsu , Tien-Hao Tang , Hua-Chou Tseng
发明人： Shiao-Shien Chen , Tsun-Lai Hsu , Tien-Hao Tang , Hua-Chou Tseng
IPC分类号： H01L21/331 , H01L21/8238 , H01L21/8249 , H01L23/60 , H01L23/62 , H01L27/02 , H01L27/06 , H01L27/092
CPC分类号： H01L27/0266 , H01L21/823814 , H01L21/8249 , H01L27/0623 , H01L27/0922
摘要： A structure of an electrostatic discharge protection circuit, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.
摘要翻译：静电放电保护电路的结构，其中在静电放电保护电路的基板中形成掩埋层，以及与埋层电连接的沉降片和漏极。因此，当静电放电保护电路被激活时，电流从源极通过掩埋层和沉降片流向漏极。电流流动路径远离栅介质层，以避免大电流损坏栅极电介质，从而提高静电放电保护电路的绝缘强度。

2. 发明授权

US06855611B2 Fabrication method of an electrostatic discharge protection circuit with a low resistant current path 有权
标题翻译：具有低电阻电流路径的静电放电保护电路的制造方法
公开(公告)号：US06855611B2
公开(公告)日：2005-02-15
申请号：US10259947
申请日：2002-09-30
申请人： Shiao-Shien Chen , Tsun-Lai Hsu , Tien-Hao Tang , Hua-Chou Tseng
发明人： Shiao-Shien Chen , Tsun-Lai Hsu , Tien-Hao Tang , Hua-Chou Tseng
IPC分类号： H01L21/331 , H01L21/8238 , H01L21/8249 , H01L23/60 , H01L23/62 , H01L27/02 , H01L27/06 , H01L27/092
CPC分类号： H01L27/0266 , H01L21/823814 , H01L21/8249 , H01L27/0623 , H01L27/0922
摘要： A fabrication method of an electrostatic discharge protection circuit is described, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.
摘要翻译：描述了静电放电保护电路的制造方法，其中在静电放电保护电路的衬底中形成掩埋层，并且还在其中形成与埋层电连接的沉降片和漏极。因此，当静电放电保护电路被激活时，电流从源极通过掩埋层和沉降片流向漏极。电流流动路径远离栅介质层，以避免大电流损坏栅极电介质，从而提高静电放电保护电路的绝缘强度。

3. 发明授权

US07253480B2 Structure and fabrication method of electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路的结构与制造方法
公开(公告)号：US07253480B2
公开(公告)日：2007-08-07
申请号：US10951373
申请日：2004-09-28
申请人： Shiao-Shien Chen , Tsun-Lai Hsu , Tien-Hao Tang , Hua-Chou Tseng
发明人： Shiao-Shien Chen , Tsun-Lai Hsu , Tien-Hao Tang , Hua-Chou Tseng
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L21/823814 , H01L21/8249 , H01L27/0623 , H01L27/0922
摘要： A structure of an electrostatic discharge protection circuit, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.
摘要翻译：静电放电保护电路的结构，其中在静电放电保护电路的基板中形成掩埋层，以及与埋层电连接的沉降片和漏极。因此，当静电放电保护电路被激活时，电流从源极通过掩埋层和沉降片流向漏极。电流流动路径远离栅介质层，以避免大电流损坏栅极电介质，从而提高静电放电保护电路的绝缘强度。

4. 发明授权

US07367113B2 Method for fabricating a transformer integrated with a semiconductor structure 有权
标题翻译：用于制造与半导体结构集成的变压器的方法
公开(公告)号：US07367113B2
公开(公告)日：2008-05-06
申请号：US11278952
申请日：2006-04-06
申请人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
发明人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
IPC分类号： H01F41/02
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.
摘要翻译：提供基板，并在其上形成顶部互连金属层和初级绕组层。然后在基板上形成具有顶部互连金属层的多个通孔露出部分的钝化层。在钝化层上形成次级绕组层和至少一个焊盘。接合焊盘通过通孔电连接到顶部互连金属层。

5. 发明申请

US20050212641A1 Method of fabricating inductor and structure formed therefrom 有权
标题翻译：制造电感器及其结构的方法
公开(公告)号：US20050212641A1
公开(公告)日：2005-09-29
申请号：US10810435
申请日：2004-03-25
申请人： Chien-Chou Hung , Hua-Chou Tseng , Tsun-Lai Hsu , Cheng-Wen Fan , Chia-Hung Chin , Ellis Lin
发明人： Chien-Chou Hung , Hua-Chou Tseng , Tsun-Lai Hsu , Cheng-Wen Fan , Chia-Hung Chin , Ellis Lin
IPC分类号： H01F5/00 , H01F41/04
CPC分类号： H01F41/041 , H01F2017/0046 , Y10T29/4902
摘要： An inductor formed on a substrate having a dielectric layer thereon is disclosed. The inductor includes a first inductor pattern, a second inductor pattern a third inductor pattern. The first inductor pattern is formed within the dielectric layer, the second inductor pattern is formed on the first inductor pattern and electrically connected thereto, and the third inductor pattern is formed on the second inductor pattern and electrically connected thereto, wherein the first inductor pattern, the second inductor pattern, and the third inductor pattern have similar pattern. Because the thickness of the inductor can be increased by forming a multi-layer inductor structure, the resistance of the inductor, therefore, is reduced.
摘要翻译：公开了一种在其上具有介电层的基板上形成的电感器。电感器包括第一电感器图案，第二电感器图案，第三电感器图案。第一电感器图案形成在电介质层内，第二电感器图案形成在第一电感器图案上并与之电连接，并且第三电感器图案形成在第二电感器图案上并与其电连接，其中第一电感器图案，第二电感器图案和第三电感器图案具有相似的图案。因为通过形成多层电感器结构可以增加电感器的厚度，因此电感器的电阻降低。

6. 发明授权

US07167072B2 Method of fabricating inductor and structure formed therefrom 有权
标题翻译：制造电感器及其结构的方法
公开(公告)号：US07167072B2
公开(公告)日：2007-01-23
申请号：US10810435
申请日：2004-03-25
申请人： Chien-Chou Hung , Hua-Chou Tseng , Tsun-Lai Hsu , Cheng-Wen Fan , Chia-Hung Chin , Ellis Lin
发明人： Chien-Chou Hung , Hua-Chou Tseng , Tsun-Lai Hsu , Cheng-Wen Fan , Chia-Hung Chin , Ellis Lin
IPC分类号： H01F5/00 , H01F27/28
CPC分类号： H01F41/041 , H01F2017/0046 , Y10T29/4902
摘要： An inductor formed on a substrate having a dielectric layer thereon is disclosed. The inductor includes a first inductor pattern, a second inductor pattern a third inductor pattern. The first inductor pattern is formed within the dielectric layer, the second inductor pattern is formed on the first inductor pattern and electrically connected thereto, and the third inductor pattern is formed on the second inductor pattern and electrically connected thereto, wherein the first inductor pattern, the second inductor pattern, and the third inductor pattern have similar pattern. Because the thickness of the inductor can be increased by forming a multi-layer inductor structure, the resistance of the inductor, therefore, is reduced.
摘要翻译：公开了一种在其上具有介电层的基板上形成的电感器。电感器包括第一电感器图案，第二电感器图案，第三电感器图案。第一电感器图案形成在电介质层内，第二电感器图案形成在第一电感器图案上并与之电连接，并且第三电感器图案形成在第二电感器图案上并与其电连接，其中第一电感器图案，第二电感器图案和第三电感器图案具有相似的图案。因为通过形成多层电感器结构可以增加电感器的厚度，因此电感器的电阻降低。

7. 发明授权

US07321285B2 Method for fabricating a transformer integrated with a semiconductor structure 有权
公开(公告)号：US07321285B2
公开(公告)日：2008-01-22
申请号：US11736565
申请日：2007-04-17
申请人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
发明人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.

8. 发明申请

US20070236320A1 METHOD FOR FABRICATING A TRANSFORMER INTEGRATED WITH A SEMICONDUCTOR STRUCTURE 有权
标题翻译：一种用半导体结构集成的变压器的方法
公开(公告)号：US20070236320A1
公开(公告)日：2007-10-11
申请号：US11736565
申请日：2007-04-17
申请人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
发明人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.
摘要翻译：提供基板，并在其上形成顶部互连金属层和初级绕组层。然后在基板上形成具有顶部互连金属层的多个通孔露出部分的钝化层。在钝化层上形成次级绕组层和至少一个焊盘。接合焊盘通过通孔电连接到顶部互连金属层。

9. 发明申请

US20070234554A1 METHOD FOR FABRICATING A TRANSFORMER INTEGRATED WITH A SEMICONDUCTOR STRUCTURE 有权
公开(公告)号：US20070234554A1
公开(公告)日：2007-10-11
申请号：US11278952
申请日：2006-04-06
申请人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
发明人： Cheng-Chou Hung , Hua-Chou Tseng , Victor-Chiang Liang , Yu-Chia Chen , Tsun-Lai Hsu
IPC分类号： H01F7/06
CPC分类号： H01F17/0006 , H01F27/2804 , H01F41/041 , H01L23/5227 , H01L24/02 , H01L2924/14 , Y10T29/49002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49128
摘要： A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.

10. 发明授权

US08581347B2 Forming bipolar transistor through fast EPI-growth on polysilicon 有权
标题翻译：通过在多晶硅上快速EPI生长形成双极晶体管
公开(公告)号：US08581347B2
公开(公告)日：2013-11-12
申请号：US12841275
申请日：2010-07-22
申请人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
发明人： Der-Chyang Yeh , Li-Weng Chang , Hua-Chou Tseng , Chih-Ping Chao
IPC分类号： H01L29/66
CPC分类号： H01L21/8249 , H01L21/8228 , H01L27/0623 , H01L27/0826
摘要： Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well.
摘要翻译：提供了一种半导体器件，其包括形成在同一衬底上的第一晶体管和第二晶体管。第一晶体管包括第一集电极，第一基极和第一发射极。第一集电器包括设置在衬底中的第一掺杂阱。第一基底包括设置在衬底上方和第一掺杂阱上方的第一掺杂层。第一发射器包括设置在第一掺杂层的一部分上的掺杂元件。第二晶体管包括第二集电极，第二基极和第二发射极。第二集电体包括衬底的掺杂部分。第二基底包括设置在衬底中并在衬底的掺杂部分上方的第二掺杂阱。第二发射器包括设置在衬底上方和第二掺杂阱上方的第二掺杂层。

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