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1. 发明申请

US20080012092A1 STRUCTURE OF CAPACITOR SET AND METHOD FOR REDUCING CAPACITANCE VARIATION BETWEEN CAPACITORS 有权
标题翻译：电容器结构和减少电容之间电容变化的方法
公开(公告)号：US20080012092A1
公开(公告)日：2008-01-17
申请号：US11309164
申请日：2006-07-04
申请人： Victor-Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
发明人： Victor-Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
IPC分类号： H01L29/00
CPC分类号： H01L28/91 , H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.
摘要翻译：描述了电容器组的结构，其包括设置在基板上的相同位置处的至少两个电容器，并且包括第一电容器和第二电容器。第一电容器包括并联电连接的多个第一电容器单元。第二电容器包括并联电连接的多个第二电容器单元。第一和第二电容器单元彼此空间上相互混合以形成阵列。

2. 发明授权

US07271428B2 Heterojunction bipolar transistor 有权
标题翻译：异质结双极晶体管
公开(公告)号：US07271428B2
公开(公告)日：2007-09-18
申请号：US11021246
申请日：2004-12-21
申请人： Cheng-Wen Fan , Hua-Chou Tseng
发明人： Cheng-Wen Fan , Hua-Chou Tseng
IPC分类号： H01L31/0328
CPC分类号： H01L29/66242 , H01L29/66318
摘要： The invention provides a heterojunction bipolar transistor comprising a substrate having a collector therein, an intrinsic base region, a first extrinsic base region, a second extrinsic base region, an emitter on the intrinsic base layer and a spacer adjacent the emitter and on the first extrinsic base region. The first extrinsic base region is adjacent the intrinsic base region and the second extrinsic base region is adjacent the first extrinsic base region on the substrate, wherein a dopant concentration of the second extrinsic base region is higher than a dopant concentration of the first extrinsic base region.
摘要翻译：本发明提供了一种异质结双极晶体管，其包括其中具有集电极的衬底，本征基极区域，第一非本征基极区域，第二非本征基极区域，本征基极层上的发射极和邻近发射极的间隔区以及与第一外部基极基地区。第一非本征基区与本征基区相邻，第二非本征基区与衬底上的第一非本征基区邻接，其中第二非本征基区的掺杂浓度高于第一非本征基区的掺杂浓度。

3. 发明申请

US20050212641A1 Method of fabricating inductor and structure formed therefrom 有权
标题翻译：制造电感器及其结构的方法
公开(公告)号：US20050212641A1
公开(公告)日：2005-09-29
申请号：US10810435
申请日：2004-03-25
申请人： Chien-Chou Hung , Hua-Chou Tseng , Tsun-Lai Hsu , Cheng-Wen Fan , Chia-Hung Chin , Ellis Lin
发明人： Chien-Chou Hung , Hua-Chou Tseng , Tsun-Lai Hsu , Cheng-Wen Fan , Chia-Hung Chin , Ellis Lin
IPC分类号： H01F5/00 , H01F41/04
CPC分类号： H01F41/041 , H01F2017/0046 , Y10T29/4902
摘要： An inductor formed on a substrate having a dielectric layer thereon is disclosed. The inductor includes a first inductor pattern, a second inductor pattern a third inductor pattern. The first inductor pattern is formed within the dielectric layer, the second inductor pattern is formed on the first inductor pattern and electrically connected thereto, and the third inductor pattern is formed on the second inductor pattern and electrically connected thereto, wherein the first inductor pattern, the second inductor pattern, and the third inductor pattern have similar pattern. Because the thickness of the inductor can be increased by forming a multi-layer inductor structure, the resistance of the inductor, therefore, is reduced.
摘要翻译：公开了一种在其上具有介电层的基板上形成的电感器。电感器包括第一电感器图案，第二电感器图案，第三电感器图案。第一电感器图案形成在电介质层内，第二电感器图案形成在第一电感器图案上并与之电连接，并且第三电感器图案形成在第二电感器图案上并与其电连接，其中第一电感器图案，第二电感器图案和第三电感器图案具有相似的图案。因为通过形成多层电感器结构可以增加电感器的厚度，因此电感器的电阻降低。

4. 发明授权

US07167072B2 Method of fabricating inductor and structure formed therefrom 有权
标题翻译：制造电感器及其结构的方法
公开(公告)号：US07167072B2
公开(公告)日：2007-01-23
申请号：US10810435
申请日：2004-03-25
申请人： Chien-Chou Hung , Hua-Chou Tseng , Tsun-Lai Hsu , Cheng-Wen Fan , Chia-Hung Chin , Ellis Lin
发明人： Chien-Chou Hung , Hua-Chou Tseng , Tsun-Lai Hsu , Cheng-Wen Fan , Chia-Hung Chin , Ellis Lin
IPC分类号： H01F5/00 , H01F27/28
CPC分类号： H01F41/041 , H01F2017/0046 , Y10T29/4902
摘要： An inductor formed on a substrate having a dielectric layer thereon is disclosed. The inductor includes a first inductor pattern, a second inductor pattern a third inductor pattern. The first inductor pattern is formed within the dielectric layer, the second inductor pattern is formed on the first inductor pattern and electrically connected thereto, and the third inductor pattern is formed on the second inductor pattern and electrically connected thereto, wherein the first inductor pattern, the second inductor pattern, and the third inductor pattern have similar pattern. Because the thickness of the inductor can be increased by forming a multi-layer inductor structure, the resistance of the inductor, therefore, is reduced.
摘要翻译：公开了一种在其上具有介电层的基板上形成的电感器。电感器包括第一电感器图案，第二电感器图案，第三电感器图案。第一电感器图案形成在电介质层内，第二电感器图案形成在第一电感器图案上并与之电连接，并且第三电感器图案形成在第二电感器图案上并与其电连接，其中第一电感器图案，第二电感器图案和第三电感器图案具有相似的图案。因为通过形成多层电感器结构可以增加电感器的厚度，因此电感器的电阻降低。

5. 发明授权

US06881640B2 Fabrication method for heterojunction bipolar transistor 有权
标题翻译：异质结双极晶体管的制造方法
公开(公告)号：US06881640B2
公开(公告)日：2005-04-19
申请号：US10655696
申请日：2003-09-05
申请人： Cheng-Wen Fan , Hua-Chou Tseng
发明人： Cheng-Wen Fan , Hua-Chou Tseng
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/66318
摘要： A fabrication method for heterojunction bipolar transistor is disclosed. The method uses ISSG oxide instead of conventional PECVD oxide so that the base/emitter interface damage can be reduced. Moreover, the invention replaces the conventional emitter-window/space mask with an emitter-window reverse-tone mask/line mask to minimize the critical dimension of emitter window. Furthermore, the invention also utilizes a two-steps extrinsic base implantation to form two extrinsic bases with different dopant concentrations so that the base resistance can be reduced.
摘要翻译：公开了一种用于异质结双极晶体管的制造方法。该方法使用ISSG氧化物代替传统的PECVD氧化物，从而可以降低基极/发射极的界面损伤。此外，本发明用发射器 - 窗口反色调掩模/线掩模替代了常规的发射窗口/空间掩模，以最小化发射器窗口的临界尺寸。此外，本发明还利用两步外部基极注入形成具有不同掺杂剂浓度的两个外在碱基，从而可以降低基极电阻。

6. 发明授权

US08114752B2 Structure of capacitor set 有权
标题翻译：电容器组的结构
公开(公告)号：US08114752B2
公开(公告)日：2012-02-14
申请号：US12701521
申请日：2010-02-06
申请人： Victor Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
发明人： Victor Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.
摘要翻译：描述了电容器组的结构，其包括设置在基板上的相同位置处的至少两个电容器，并且包括第一电容器和第二电容器。第一电容器包括并联电连接的多个第一电容器单元。第二电容器包括并联电连接的多个第二电容器单元。第一和第二电容器单元彼此空间上相互混合以形成阵列。

7. 发明申请

US20100140741A1 STRUCTURE OF CAPACITOR SET 有权
标题翻译：电容器结构
公开(公告)号：US20100140741A1
公开(公告)日：2010-06-10
申请号：US12701521
申请日：2010-02-06
申请人： Victor Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
发明人： Victor Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
IPC分类号： H01L29/92
CPC分类号： H01L28/91 , H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.
摘要翻译：描述了电容器组的结构，其包括设置在基板上的相同位置处的至少两个电容器，并且包括第一电容器和第二电容器。第一电容器包括并联电连接的多个第一电容器单元。第二电容器包括并联电连接的多个第二电容器单元。第一和第二电容器单元彼此空间上相互混合以形成阵列。

8. 发明申请

US20050110044A1 Fabrication method for heterojunction bipolar transistor 有权
公开(公告)号：US20050110044A1
公开(公告)日：2005-05-26
申请号：US11021246
申请日：2004-12-21
申请人： Cheng-Wen Fan , Hua-Chou Tseng
发明人： Cheng-Wen Fan , Hua-Chou Tseng
IPC分类号： H01L21/331 , H01L29/739
CPC分类号： H01L29/66242 , H01L29/66318
摘要： A fabrication method for heterojunction bipolar transistor is disclosed. The method uses ISSG oxide instead of conventional PECVD oxide so that the base/emitter interface damage can be reduced. Moreover, the invention replaces the conventional emitter-window/space mask with an emitter-window reverse-tone mask/line mask to minimize the critical dimension of emitter window. Furthermore, the invention also utilizes a two-steps extrinsic base implantation to form two extrinsic bases with different dopant concentrations so that the base resistance can be reduced.

9. 发明申请

US20050051797A1 FABRICATION METHOD FOR HETEROJUNCTION BIPOLAR TRANSISTOR 有权
标题翻译：异相双极晶体管的制造方法
公开(公告)号：US20050051797A1
公开(公告)日：2005-03-10
申请号：US10655696
申请日：2003-09-05
申请人： Cheng-Wen Fan , Hua-Chou Tseng
发明人： Cheng-Wen Fan , Hua-Chou Tseng
IPC分类号： H01L21/331 , H01L29/739 , H01L21/8222 , H01L31/0328
CPC分类号： H01L29/66242 , H01L29/66318
摘要： A fabrication method for heterojunction bipolar transistor is disclosed. The method uses ISSG oxide instead of conventional PECVD oxide so that the base/emitter interface damage can be reduced. Moreover, the invention replaces the conventional emitter-window/space mask with an emitter-window reverse-tone mask/line mask to minimize the critical dimension of emitter window. Furthermore, the invention also utilizes a two-steps extrinsic base implantation to form two extrinsic bases with different dopant concentrations so that the base resistance can be reduced.
摘要翻译：公开了一种用于异质结双极晶体管的制造方法。该方法使用ISSG氧化物代替传统的PECVD氧化物，从而可以降低基极/发射极的界面损伤。此外，本发明用发射器 - 窗口反色调掩模/线掩模替代了常规的发射窗口/空间掩模，以最小化发射器窗口的临界尺寸。此外，本发明还利用两步外部基极注入形成具有不同掺杂剂浓度的两个外在碱基，从而可以降低基极电阻。

10. 发明授权

US08133792B2 Method for reducing capacitance variation between capacitors 有权
标题翻译：降低电容器电容变化的方法
公开(公告)号：US08133792B2
公开(公告)日：2012-03-13
申请号：US11309164
申请日：2006-07-04
申请人： Victor-Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
发明人： Victor-Chiang Liang , Chien-Kuo Yang , Hua-Chou Tseng , Chun-Yao Ko , Cheng-Wen Fan , Yu-Ho Chiang , Chih-Yuh Tzeng
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.
摘要翻译：描述了电容器组的结构，其包括设置在基板上的相同位置处的至少两个电容器，并且包括第一电容器和第二电容器。第一电容器包括并联电连接的多个第一电容器单元。第二电容器包括并联电连接的多个第二电容器单元。第一和第二电容器单元彼此空间上相互混合以形成阵列。

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