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1. 发明授权

US08630317B2 Memory system with calibrated data communication 有权
标题翻译：具有校准数据通信的存储系统
公开(公告)号：US08630317B2
公开(公告)日：2014-01-14
申请号：US13447080
申请日：2012-04-13
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： H04J3/06 , G06F1/12
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
摘要翻译：集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。

2. 发明授权

US08458385B2 Chip having register to store value that represents adjustment to reference voltage 有权
标题翻译：具有寄存器的芯片存储表示对参考电压的调整的值
公开(公告)号：US08458385B2
公开(公告)日：2013-06-04
申请号：US13535228
申请日：2012-06-27
申请人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
发明人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F13/00 , G05F1/10
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： A chip includes a receiver circuit that uses a reference voltage to receive a data signal such that a logic level of the received data signal is determined using the reference voltage, and a register to store a value that represents an adjustment to the reference voltage.
摘要翻译：芯片包括接收器电路，其使用参考电压来接收数据信号，使得使用参考电压确定接收到的数据信号的逻辑电平，以及寄存器，用于存储表示对参考电压的调整的值。

3. 发明授权

US08428196B2 Equalizing receiver 有权
标题翻译：均衡接收机
公开(公告)号：US08428196B2
公开(公告)日：2013-04-23
申请号：US13469685
申请日：2012-05-11
申请人： Vladimir M. Stojanovic , Mark A. Horowitz , Jared L. Zerbe , Anthony Bessios , Andrew C. C. Ho , Jason C. Wei , Grace Tsang , Bruno W. Garlepp
发明人： Vladimir M. Stojanovic , Mark A. Horowitz , Jared L. Zerbe , Anthony Bessios , Andrew C. C. Ho , Jason C. Wei , Grace Tsang , Bruno W. Garlepp
IPC分类号： H04L27/06
CPC分类号： H04L25/03057 , H04L7/0276 , H04L25/063 , H04L25/497 , H04L2025/03369 , H04L2025/03503
摘要： A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.
摘要翻译：描述信令系统。信令系统包括发送设备，包括部分响应接收电路的接收设备以及耦合发送设备和接收设备的信令路径。接收设备观察来自信令路径的均衡信号，并且包括使用来自最近先前解析的符号的反馈来采样当前输入符号的电路。发送装置通过基于与最近先前分辨的符号值不相关的一个或多个数据值应用加权来均衡发送数据以发送均衡信号。

4. 发明授权

US08344475B2 Integrated circuit heating to effect in-situ annealing 有权
标题翻译：集成电路加热实现原位退火
公开(公告)号：US08344475B2
公开(公告)日：2013-01-01
申请号：US12859554
申请日：2010-08-19
申请人： Ian P. Shaeffer , Gary B. Bronner , Brent S. Haukness , Kevin S. Donnelly , Frederick A. Ware , Mark A. Horowitz
发明人： Ian P. Shaeffer , Gary B. Bronner , Brent S. Haukness , Kevin S. Donnelly , Frederick A. Ware , Mark A. Horowitz
IPC分类号： H01L29/00
CPC分类号： G11C16/26 , G11C7/04 , G11C13/0002 , G11C13/0033 , G11C13/0035 , G11C16/06 , H01L21/324
摘要： In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.
摘要翻译：在具有存储器件的系统中，在系统操作期间检测到事件。响应于检测到事件，存储器件被加热以反转存储器件的使用中的劣化。在另一系统中，存储器件被加热以与系统的另一个存储器件内的数据访问操作的执行同时反向使用所引起的降级。在具有耦合到第一和第二存储器设备的存储器控制器的另一系统中，响应于确定在第一存储器设备内需要维护操作，将数据从第一存储器设备抽出到第二存储器设备。

5. 发明申请

US20120300097A1 VARIABLE IMAGING ARRANGEMENTS AND METHODS THEREFOR 有权
标题翻译：可变成像装置及其方法
公开(公告)号：US20120300097A1
公开(公告)日：2012-11-29
申请号：US13542575
申请日：2012-07-05
申请人： Yi-Ren NG , Patrick M. Hanrahan , Mark A. Horowitz , Marc S. Levoy
发明人： Yi-Ren NG , Patrick M. Hanrahan , Mark A. Horowitz , Marc S. Levoy
IPC分类号： H04N5/225
CPC分类号： H04N5/2254 , G02B3/0056 , G02B27/0075 , H01L27/14627 , H04N5/2173 , H04N5/23212 , H04N5/23232 , H04N5/23293 , H04N13/236
摘要： Various approaches to imaging involve selecting directional and spatial resolution. According to an example embodiment, images are computed using an imaging arrangement to facilitate selective directional and spatial aspects of the detection and processing of light data. Light passed through a main lens is directed to photosensors via a plurality of microlenses. The separation between the microlenses and photosensors is set to facilitate directional and/or spatial resolution in recorded light data, and facilitating refocusing power and/or image resolution in images computed from the recorded light data. In one implementation, the separation is varied between zero and one focal length of the microlenses to respectively facilitate spatial and directional resolution (with increasing directional resolution, hence refocusing power, as the separation approaches one focal length).
摘要翻译：成像的各种方法涉及选择方向和空间分辨率。根据示例实施例，使用成像装置来计算图像，以促进光数据的检测和处理的选择性方向和空间方面。通过主透镜的光通过多个微透镜被引向光传感器。微透镜和光电传感器之间的间隔被设置为有助于记录的光数据中的方向和/或空间分辨率，并且促进从记录的光数据计算的图像中的重新聚焦功率和/或图像分辨率。在一个实施方式中，分离在微透镜的零和一个焦距之间变化，以分别促进空间和方向分辨率（随着方向分辨率的提高，因此随着分离接近一个焦距，重新聚焦功率）。

6. 发明授权

US08311176B2 Clock and data recovery employing piece-wise estimation on the derivative of the frequency 有权
标题翻译：使用对频率导数进行分段估计的时钟和数据恢复
公开(公告)号：US08311176B2
公开(公告)日：2012-11-13
申请号：US12441003
申请日：2007-09-05
申请人： Hae-Chang Lee , Thomas H. Greer, III , Jade M. Kizer , Brian S. Leibowitz , Mark A. Horowitz
发明人： Hae-Chang Lee , Thomas H. Greer, III , Jade M. Kizer , Brian S. Leibowitz , Mark A. Horowitz
IPC分类号： H03D3/24
CPC分类号： H04L7/0012 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0008 , H04L7/0331 , H04L7/0337
摘要： A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.
摘要翻译：一种用于执行时钟和数据恢复的系统和方法。系统根据数据发送器时钟的频率和接收机时钟15的频率之间的偏移的变化率的至少三个估计来设置恢复的时钟信号30的相位。

7. 发明申请

US20120268199A1 Chip Having Register to Store Value that Represents Adjustment to Reference Voltage 有权
标题翻译：芯片有注册存储代表调整参考电压的值
公开(公告)号：US20120268199A1
公开(公告)日：2012-10-25
申请号：US13535228
申请日：2012-06-27
申请人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
发明人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： H01L25/00
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： A chip includes a receiver circuit that uses a reference voltage to receive a data signal such that a logic level of the received data signal is determined using the reference voltage, and a register to store a value that represents an adjustment to the reference voltage.
摘要翻译：芯片包括接收器电路，其使用参考电压来接收数据信号，使得使用参考电压确定接收到的数据信号的逻辑电平，以及寄存器，用于存储表示对参考电压的调整的值。

8. 发明申请

US20120229682A1 Correction of Optical Abberations 有权
标题翻译：光学补偿的校正
公开(公告)号：US20120229682A1
公开(公告)日：2012-09-13
申请号：US13466338
申请日：2012-05-08
申请人： Yi-Ren NG , Patrick M. Hanrahan , Mark A. Horowitz , Marc S. Levoy
发明人： Yi-Ren NG , Patrick M. Hanrahan , Mark A. Horowitz , Marc S. Levoy
IPC分类号： H04N5/217 , G06K9/40
CPC分类号： H04N9/646 , H04N5/3572
摘要： Digital images are computed using an approach for correcting lens aberration. According to an example embodiment of the present invention, a digital imaging arrangement implements microlenses to direct light to photosensors that detect the light and generate data corresponding to the detected light. The generated data is used to compute an output image, where each output image pixel value corresponds to a selective weighting and summation of a subset of the detected photosensor values. The weighting is a function of characteristics of the imaging arrangement. In some applications, the weighting reduces the contribution of data from photosensors that contribute higher amounts of optical aberration to the corresponding output image pixel.
摘要翻译：使用用于校正透镜像差的方法来计算数字图像。根据本发明的示例性实施例，数字成像装置实现微透镜以将光引导到检测光的光电传感器并产生对应于检测到的光的数据。生成的数据用于计算输出图像，其中每个输出图像像素值对应于检测到的光电传感器值的子集的选择性加权和求和。加权是成像装置的特征的函数。在一些应用中，加权减少了对相应的输出图像像素贡献更大量的光学像差的光电传感器的数据的贡献。

9. 发明授权

US08243157B2 Correction of optical aberrations 有权
标题翻译：矫正光学像差
公开(公告)号：US08243157B2
公开(公告)日：2012-08-14
申请号：US12278708
申请日：2007-02-06
申请人： Yi-Ren Ng , Patrick M. Hanrahan , Mark A. Horowitz , Marc S. Levoy
发明人： Yi-Ren Ng , Patrick M. Hanrahan , Mark A. Horowitz , Marc S. Levoy
IPC分类号： H04N5/228 , G03B13/00 , H04N5/232
CPC分类号： G02B7/08 , G02B3/0006 , G02B3/0056 , G02B3/0075 , G02B27/0075 , H04N5/2253 , H04N5/23212
摘要： Digital images are computed using an approach for correcting lens aberration. According to an example embodiment of the present invention, a digital imaging arrangement implements microlenses to direct light to photosensors that detect the light and generate data corresponding to the detected light. The generated data is used to compute an output image, where each output image pixel value corresponds to a selective weighting and summation of a subset of the detected photosensor values. The weighting is a function of characteristics of the imaging arrangement. In some applications, the weighting reduces the contribution of data from photosensors that contribute higher amounts of optical aberration to the corresponding output image pixel.
摘要翻译：使用用于校正透镜像差的方法来计算数字图像。根据本发明的示例性实施例，数字成像装置实现微透镜以将光引导到检测光的光电传感器并产生对应于检测到的光的数据。生成的数据用于计算输出图像，其中每个输出图像像素值对应于检测到的光电传感器值的子集的选择性加权和求和。加权是成像装置的特征的函数。在一些应用中，加权减少了对相应的输出图像像素贡献更大量的光学像差的光电传感器的数据的贡献。

10. 发明授权

US08199859B2 Integrating receiver with precharge circuitry 有权
标题翻译：将接收机与预充电电路集成
公开(公告)号：US08199859B2
公开(公告)日：2012-06-12
申请号：US12897661
申请日：2010-10-04
申请人： Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
发明人： Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
IPC分类号： H03D1/24 , H03K7/02
CPC分类号： H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要： An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.
摘要翻译：集成电路器件包括具有输入端的读出放大器，用于接收表示当前位的当前信号。读出放大器将产生关于当前位的逻辑电平的判定。该集成电路器件还包括一个电路，用于通过向读出放大器的输入端施加代表先前位的先前信号的一部分来对读出放大器的输入进行预充电。集成电路器件还包括耦合到读出放大器以输出逻辑电平的锁存器。

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