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    • 1. 发明授权
    • Bipolar transistor and method for producing same
    • 双极晶体管及其制造方法
    • US06465318B1
    • 2002-10-15
    • US09787571
    • 2001-08-02
    • Karl-Ernst EhwaldBernd TillackBernd HeinemannDieter KnollDirk Wolansky
    • Karl-Ernst EhwaldBernd TillackBernd HeinemannDieter KnollDirk Wolansky
    • H01L21331
    • H01L29/66287H01L29/7322
    • This invention relates to a bi-polar transistor and a procedure for its manufacture. The task of the invention is to propose a bi-polar transistor and a procedure for its manufacture that eliminates the disadvantages of conventional arrangements for a simple polysilicon technology with differential epitaxy for the manufacture of the base, in order to further improve especially the high-speed properties of a bi-polar transistor, to produce highly conductive connections between the metal contacts and the active (inner) transistor region as well as a minimized passive transistor surface, and to simultaneously avoid any additional process complexity and increased contact resistance. This invention resolves the task in that, by creating suitable epitaxy process conditions, the polysilicon layer is deposited on the insulator zone with a greater thickness than the epitaxy layer in the active transistor zone. The greater thickness of the polysilicon layer as compared to the epitaxial layer is achieved by using a very low temperature for the deposition of a part of or the entire buffer layer. The use of a low temperature for the deposition allows a better nucleation of the insulator layer and a reduction of the idle time for the deposition. This allows achieving a greater thickness on the insulator layer as compared with the active transistor zone.
    • 本发明涉及双极晶体管及其制造方法。 本发明的任务是提出一种双极晶体管及其制造方法,其消除了用于制造基底的具有差分外延的简单多晶硅技术的常规布置的缺点, 双极晶体管的速度特性,以在金属触点和有源(内部)晶体管区域之间产生高导电连接以及最小化的无源晶体管表面,同时避免任何额外的工艺复杂性和增加的接触电阻。 本发明解决了通过创建合适的外延工艺条件的工作,多晶硅层以比有源晶体管区中的外延层更大的厚度沉积在绝缘体区上。 与外延层相比,多晶硅层的厚度越大,通过使用非常低的温度来沉积一部分或整个缓冲层来实现。 使用低温进行沉积允许绝缘体层的更好的成核和减少沉积的空闲时间。 与有源晶体管区域相比,这允许在绝缘体层上实现更大的厚度。
    • 2. 发明授权
    • Apparatus for low-temperature epitaxy on a plurality semiconductor substrates
    • 用于在多个半导体衬底上进行低温外延的装置
    • US08932405B2
    • 2015-01-13
    • US11579276
    • 2005-05-10
    • Thomas GrabollaGeorge RitterBernd Tillack
    • Thomas GrabollaGeorge RitterBernd Tillack
    • C23C16/00C23C16/54C30B25/08
    • C23C16/54C30B25/08
    • A reactor arrangement for layer deposition on a plurality of substrates (hereafter substrates) comprising a first reactor chamber for simultaneous cleaning the substrates, at least one second reactor chamber for depositing at least one layer on each of the substrates, a first heating device for setting the substrate temperature of the substrates in the first reactor chamber, a second heating device for setting the substrate temperature of the substrates in the second reactor chamber, a device for producing a gas atmosphere of predetermined composition and predetermined pressure, a transport device for transporting the substrates simultaneously from the first to the second reactor chamber, and a control device for controlling the heating devices and device for producing the gas atmosphere in such a way that the substrates are moved or stored in an interruption-free manner in a reducing gas atmosphere as long as the substrate temperature is above critical temperature Tc.
    • 一种反应器装置,用于在多个基板(以下称为基板)上层压沉积,该基板包括用于同时清洁基板的第一反应器室,用于在每个基板上沉积至少一层的至少一个第二反应室,用于设定的第一加热装置 第一反应器室中的基板的基板温度,用于设定第二反应器室中的基板的基板温度的第二加热装置,用于制造预定组成和预定压力的气体气氛的装置,用于输送 基板同时从第一反应室到第二反应室,以及控制装置,用于控制加热装置和用于产生气体气氛的装置,使得基板在还原气体气氛中以无中断的方式移动或储存,如 只要衬底温度高于临界温度Tc。
    • 4. 发明授权
    • Layers in substrate wafers
    • 衬底晶圆层
    • US07595534B2
    • 2009-09-29
    • US10433969
    • 2001-12-06
    • Bernd HeinemannKarl-Ernst EhwaldDieter KnollBernd TillackDirk WolanskyPeter Schley
    • Bernd HeinemannKarl-Ernst EhwaldDieter KnollBernd TillackDirk WolanskyPeter Schley
    • H01L29/76H01L29/94H01L31/062H01L31/113
    • H01L21/74H01L21/26506H01L21/823807H01L21/823892H01L29/1083
    • The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve, on the one hand, an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a non-destructive manner. To these ends, the invention provides that in a highly resistive p-Si substrate (2) with one or more buried high-carbon Si layers (3) under an epitaxial layer and with the Si cap layer (4), an implantation dose, which is greater in comparison to conventional substrate wafers, is used for retrograde trough profiles by suppressing the dopant diffusion as well as the generation of defects when remedying implant defects, thereby achieving a reduction of the trough resistance, and finally, an increase in the resistance to latch-up.
    • 本发明涉及衬底晶片中的层。 本发明的目的是提供衬底晶片中的层,其中克服了常规组件的缺点,以便一方面实现具有相对较低成本的高度缩放的数字CMOS电路中的闩锁的适当电阻,以及 另一方面,为了确保模拟高频电路的低衬底损耗/耦合,此外,以非破坏性的方式影响组件行为。 为此,本发明提供了在具有一个或多个掩埋的高碳Si层(3)的外延层和Si覆盖层(4)下的高电阻p-Si衬底(2)中的注入剂量, 与传统的基板晶片相比,通过抑制掺杂剂扩散以及在补偿注入缺陷时产生缺陷而用于逆向槽型材,从而实现了谷电阻的降低,最后增加了电阻 闭锁
    • 5. 发明授权
    • Method and device for the production of thin epitaxial semiconductor layers
    • 用于生产薄外延半导体层的方法和装置
    • US07244667B2
    • 2007-07-17
    • US10484975
    • 2002-07-25
    • Bernd TillackDirk WolanskyGeorg RitterThomas Grabolla
    • Bernd TillackDirk WolanskyGeorg RitterThomas Grabolla
    • H01L21/205
    • H01L21/02529C23C16/0218C23C16/54H01L21/02532H01L21/0262H01L21/02658
    • System for producing diffusion-inhibiting epitaxial semiconductor layers, by means of which thin diffusion-inhibiting, epitaxial semiconductor layers can be produced on large semiconductor substrates at a high throughput.The surfaces of the semiconductor substrates to be coated are first cleaned, and the substrates are then heated in a low pressure batch reactor to a first temperature (prebake temperature). The surfaces to be coated are next subjected to a hydrogen prebake operation at a first reactor pressure. In the next step the semiconductor substrates are heated in a low pressure hot or warm wall batch reactor to a second temperature (deposition temperature) lower than the first temperature, and after a condition of thermodynamic equilibrium is reached the diffusion-inhibiting semiconductor layers are deposited on the surfaces to be coated in a chemical gaseous deposition process (CVD) at a second reactor pressure higher than, equal to or lower than the first reactor pressure.
    • 用于制造扩散抑制外延半导体层的系统,通过该系统,可以在大的半导体衬底上以高通量产生薄的扩散抑制性外延半导体层。 首先清洁待涂覆的半导体衬底的表面,然后将衬底在低压间歇反应器中加热到第一温度(预烘烤温度)。 待涂覆的表面接下来在第一反应器压力下进行氢预烘烤操作。 在下一步骤中,将半导体衬底在低压热或温壁间歇反应器中加热到低于第一温度的第二温度(沉积温度),并且在达到热力学平衡条件之后,沉积扩散抑制半导体层 在高于等于或低于第一反应器压力的第二反应器压力下在化学气相沉积工艺(CVD)中待涂覆的表面上。
    • 8. 发明申请
    • MICROELECTRONIC COMPONENT
    • 微电子元件
    • US20130026659A1
    • 2013-01-31
    • US13639370
    • 2011-03-22
    • Mehmet KaynakBernd TillackRene Scholz
    • Mehmet KaynakBernd TillackRene Scholz
    • H01L23/522H01L21/768
    • B81C1/00587B81B2207/015B81B2207/07B81C2201/014
    • A method for producing a MEMS component including the steps of simultaneously embedding structure elements during producing the multi-level conductive path layer stack which structure elements are to be subsequently exposed, subsequently producing a recess that extends from a substrate backside to the multi-level conductive path layer stack, exposing the micromechanical structure elements in the multi-level conductive path layer stack through the recess. In order to increase process precision a reference mask for defining a lateral position or a lateral extension of the micromechanical structure elements to be exposed is produced, wherein the reference mask is either arranged on the substrate front side between the substrate and the multi-level conductive path layer stack or in a layer of the multi-level conductive path layer stack which layer is more proximal to the substrate than the structure element to be exposed.
    • 一种用于制造MEMS部件的方法,包括以下步骤:在制造多级导电路径层堆叠期间同时嵌入结构元件,该结构元件随后将被暴露,随后产生从背衬延伸到多层导电 路径层堆叠,通过凹槽暴露多层导电路径层堆叠中的微机械结构元件。 为了提高加工精度,产生用于限定要暴露的微机械结构元件的横向位置或横向延伸的参考掩模,其中参考掩模或者被布置在基板和多层导电 路径层堆叠或者在多层导电路径层堆叠的层中,该层比要暴露的结构元件更靠近衬底。
    • 9. 发明授权
    • Apparatus for forming and/or sealing a packaging unit
    • 用于形成和/或密封包装单元的装置
    • US06745543B2
    • 2004-06-08
    • US10150925
    • 2002-05-21
    • Bernd TillackNorbert DietrichHans Bernd Dreier
    • Bernd TillackNorbert DietrichHans Bernd Dreier
    • B65B700
    • B29C65/08B29C65/7443B29C65/7451B29C66/1122B29C66/43121B29C66/81417B29C66/81419B29C66/81433B29C66/8322B29L2031/7128B65B1/18B65B7/025B65B51/225
    • The present invention refers to an apparatus and a method for forming a packaging unit consisting of an endless hose, or for sealing a prefabricated packaging unit, comprising an ultrasonic welding device including an anvil and a sonotrode, which are movable towards each other, and a means for positioning the hose material to be welded between the anvil and the sonotrode. In accordance with the present invention it is suggested that the anvil comprises two anvil parts which are movable relative to one another in the direction of the sonotrode, one of said anvil parts being implemented as a sealing anvil and the other part being implemented as a separating anvil. Hence, the apparatus according to the present invention permits the production of packaging units which end directly at the weld, i.e. in the case of which no length section of the foil material projects outwardly beyond the weld. The method according to the present invention is characterized in that the material of the endless hose or of the packaging unit projecting beyond the weld is cut off directly adjacent to or in said weld.
    • 本发明涉及一种用于形成由环形软管或用于密封预制包装单元的包装单元的装置和方法,包括可彼此移动的包括砧和超声波发生器的超声波焊接装置,以及 用于将要焊接的软管材料定位在砧座和超声波发生器之间的装置。 根据本发明,提出了砧座包括两个砧座部件,它们可以在超声焊丝的方向上相对于彼此移动,所述砧座部件中的一个被实施为密封砧座,另一部分被实施为分离 砧。 因此,根据本发明的设备允许生产直接在焊接处终止的包装单元,即在箔材料的长度不超过焊缝的情况下。 根据本发明的方法的特征在于,环形软管或突出超过焊缝的包装单元的材料被直接切割在邻近或在所述焊缝中。