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81. 发明授权

US06221680B1 Patterned recess formation using acid diffusion 失效
标题翻译：使用酸扩散形成图形凹陷
公开(公告)号：US06221680B1
公开(公告)日：2001-04-24
申请号：US09127132
申请日：1998-07-31
申请人： Mark C. Hakey , Steven J. Holmes , David Horak , Toshiharu Furukawa
发明人： Mark C. Hakey , Steven J. Holmes , David Horak , Toshiharu Furukawa
IPC分类号： H01L2100
CPC分类号： H01L21/0273 , G03F7/094 , H01L21/02129 , H01L21/02271 , H01L21/312 , H01L21/31625 , H01L27/10861
摘要： The present invention relates to a method for providing patterned recess formation in a previously recessed area of a semiconductor structure, i.e. DRAM trench capacitor, using acid diffusion to selectively activate some, but not all of the acid sensitive material that is filled within the recessed areas of such structures. By employing the method of the present invention, it is possible to recess all the previously recessed areas at the same time providing the same level of recessed acid sensitive material within the previous recessed areas, recess some of the previously recessed areas to a desired level leaving other portions of the structure unrecessed, or recessing the previously recessed areas to contain different levels of the acid sensitive material.
摘要翻译：本发明涉及一种用于在半导体结构（即DRAM沟槽电容器）的预先凹入的区域中提供图案化的凹陷形成的方法，其使用酸扩散来选择性地激活填充在凹陷区域内的一些但不是全部的酸敏感材料的这种结构。通过采用本发明的方法，可以同时在所有先前的凹陷区域内提供相同水平的凹入的酸敏感材料，同时将所有先前凹陷的区域都凹进，将一些先前凹陷的区域凹入到期望的水平位置结构的其他部分不能被加工，或者使先前凹陷的区域凹陷以包含不同水平的酸敏感材料。

82. 发明授权

US06190988B1 Method for a controlled bottle trench for a dram storage node 失效
标题翻译：一种用于剧烈储存节点的受控瓶沟的方法
公开(公告)号：US06190988B1
公开(公告)日：2001-02-20
申请号：US09086174
申请日：1998-05-28
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , William H. Ma , James M. Never
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , William H. Ma , James M. Never
IPC分类号： H01L2120
CPC分类号： H01L27/1087
摘要： A bottle-shaped trench capacitor with a buried plate is formed in a controlled etch process. The bottle-shape is fabricated by etching deep trenches from a layered substrate, using the layers as a mask, and covering the side walls of the substrate with protective oxide and nitride layers. With the side walls covered, deep trench etching is then resumed, and a lower trench portion, below the protective layers of the side wall are formed. By diffusing a first dopant in the lower portion of the deep trench region, using the side wall protective layers as a mask, an etch stop is established for a wet etch process at the p/n junction established by the first dopant. The width of the lower trench portion is regulated by the time and temperature of the diffusion. Removing the doped material and applying a second dopant to the lower trench portion establishes a continuous buried plate region between trenches. A capacitor is formed by applying an insulating layer to the trench and filling with a conductor.
摘要翻译：在受控蚀刻工艺中形成具有掩埋板的瓶形沟槽电容器。通过使用这些层作为掩模蚀刻来自分层衬底的深沟槽，并用保护的氧化物和氮化物层覆盖衬底的侧壁来制造瓶形。在侧壁被覆盖的情况下，然后恢复深沟槽蚀刻，并且形成在侧壁的保护层下方的下沟槽部分。通过在深沟槽区域的下部扩散第一掺杂剂，使用侧壁保护层作为掩模，建立了在由第一掺杂剂建立的p / n结处的湿蚀刻工艺的蚀刻停止。下沟槽部分的宽度由扩散的时间和温度来调节。去除掺杂材料并向下沟槽部分施加第二掺杂剂在沟槽之间建立连续的掩埋板区域。通过向沟槽施加绝缘层并填充导体来形成电容器。

83. 发明授权

US06184151B2 Method for forming cornered images on a substrate and photomask formed thereby 失效
标题翻译：在基板上形成圆角图像的方法和由此形成的光掩模
公开(公告)号：US06184151B2
公开(公告)日：2001-02-06
申请号：US09275541
申请日：1999-03-24
申请人： William J. Adair , Richard A. Ferguson , Mark C. Hakey , Steven J. Holmes , David V. Horak , Robert K. Leidy , William Hsioh-Lien Ma , Ronald M. Martino , Song Peng
发明人： William J. Adair , Richard A. Ferguson , Mark C. Hakey , Steven J. Holmes , David V. Horak , Robert K. Leidy , William Hsioh-Lien Ma , Ronald M. Martino , Song Peng
IPC分类号： H01L21461
CPC分类号： H01L27/10864 , H01L21/0332 , H01L21/0334 , Y10S438/942
摘要： A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating cornered images wherever the first and second layer intersect and in the open areas between the lines. Methods are proposed for developing the square intersecting areas and the square angle areas defined by the openings. Additionally, a photomask is disclosed in which the length and width of the cornered images are independently patterned using the two-exposure process.
摘要翻译：公开了一种在光刻工艺中形成正方形形状图像的方法，其中沿第一方向延伸的第一多条线被限定在第一，通常是牺牲层中，然后定义第二抗蚀剂，其中线以相交图案到第一层的那些，从而在第一和第二层交叉的任何地方以及在线之间的开放区域中产生拐角图像。提出了用于显影方形交叉区域和由开口限定的方角区域的方法。此外，公开了一种光掩模，其中使用双曝光工艺独立地对角形图像的长度和宽度进行图案化。

84. 发明授权

US6150256A Method for forming self-aligned features 失效
标题翻译：形成自对准特征的方法
公开(公告)号：US6150256A
公开(公告)日：2000-11-21
申请号：US183338
申请日：1998-10-30
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： H01L21/027 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76825 , H01L21/0274 , H01L21/76802 , H01L21/76805 , H01L21/76811
摘要： The present invention provides for an improved method of creating vias and trenches during microchip fabrication. According to the invention, the vias and trenches are self-aligned during the photolithography process by using two layers of specially selected resists and exposing the resists such that the lower resist is exposed only where an opening has been formed in the upper resist layer. This self-aligning enables the vias to be printed as elongated shapes, which allows for the use of particularly effective image enhancement techniques. The invention further provides a simplified procedure for creating vias and trenches, in that only one etch step is required to simultaneously create both vias and trenches. An alternative embodiment of the invention allows looped or linked images, such as those printed using image enhancement techniques, to be trimmed to form isolated features.
摘要翻译：本发明提供了一种在微芯片制造期间产生通孔和沟槽的改进方法。根据本发明，通过使用两层特别选择的抗蚀剂，在光刻工艺期间，通孔和沟槽是自对准的，并且使抗蚀剂曝光，使得下抗蚀剂仅在上抗蚀剂层中形成开口的地方露出。这种自对准使通孔能够被印制成细长的形状，这允许使用特别有效的图像增强技术。本发明还提供了一种用于产生通孔和沟槽的简化过程，因为仅需要一个蚀刻步骤来同时产生通孔和沟槽。本发明的替代实施例允许将被修剪以形成隔离特征的循环或链接的图像，诸如使用图像增强技术印刷的图像。

85. 发明授权

US6007968A Method for forming features using frequency doubling hybrid resist and device formed thereby 失效
标题翻译：使用倍频混合抗蚀剂形成特征的方法和由此形成的器件
公开(公告)号：US6007968A
公开(公告)日：1999-12-28
申请号：US959779
申请日：1997-10-29
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： G03F1/00 , G03F7/038 , G03F7/20 , H01L21/027 , H01L21/02 , G03C5/00
CPC分类号： G03F7/70466 , G03F7/038 , H01L21/0274 , G03F7/2022
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art by providing a method to form unlinked features using hybrid resist. The method uses a trim process in order to trim the linking features from the "loops" formed by the hybrid resist. This allows the method to form a plurality of unlinked features rather than the loops. In order to trim the ends, a relatively larger trim area is formed adjacent the narrow feature line, either by a second exposure step or by utilizing a grey scale reticle. The broader or wider open area allows features to be formed in the narrow feature lines and being trimmed from the relatively large areas, thereby resulting in district features rather than loops.
摘要翻译：本发明的优选实施例通过提供使用混合抗蚀剂形成不连接特征的方法来克服现有技术的局限性。该方法使用修剪工艺来修剪由混合抗蚀剂形成的“环”的连接特征。这允许该方法形成多个未链接的特征而不是循环。为了修剪端部，通过第二曝光步骤或通过利用灰度光罩，形成与窄特征线相邻的相对较大的修整区域。更宽或更宽的开放区域允许在窄特征线中形成特征并且从相对较大的区域修剪特征，从而导致区域特征而不是环。

86. 发明授权

US5998835A High performance MOSFET device with raised source and drain 失效
标题翻译：高性能MOSFET器件，具有升高的源极和漏极
公开(公告)号：US5998835A
公开(公告)日：1999-12-07
申请号：US24840
申请日：1998-02-17
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma , Jack A. Mandelman
IPC分类号： H01L21/225 , H01L21/336 , H01L29/78 , H01L29/50
CPC分类号： H01L29/66613 , H01L29/66621 , H01L29/7834 , H01L21/2255
摘要： A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion layer is connected to the edge of the device channel by extending the diffusion layer along the side wall of the trench and under a portion of the trench.
摘要翻译：一种MOSFET器件及其制造方法。该器件具有形成在硅衬底中的沟槽。设备的通道位于沟槽的底部。扩散层邻近沟槽的相对侧形成。通过沿着沟槽的侧壁和沟槽的一部分延伸扩散层，将每个扩散层连接到器件沟道的边缘。

87. 发明授权

US07838943B2 Shared gate for conventional planar device and horizontal CNT 有权
标题翻译：常规平面器件和水平CNT的共用门
公开(公告)号：US07838943B2
公开(公告)日：2010-11-23
申请号：US11161146
申请日：2005-07-25
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
IPC分类号： H01L21/70
CPC分类号： H01L21/823412 , B01J23/74 , B01J37/0238 , B82Y10/00 , H01L21/7624 , H01L21/823437 , H01L27/286 , H01L51/0048 , H01L51/0545 , H01L51/055 , Y10S977/742 , Y10S977/762 , Y10S977/763
摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
摘要翻译：在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管晶体管位于至少一个平面半导体器件的栅极之上。

88. 发明授权

US07601205B2 Carbon nanotubes as low voltage field emission sources for particle precipitators 失效
标题翻译：碳纳米管作为颗粒除尘器的低电压场发射源
公开(公告)号：US07601205B2
公开(公告)日：2009-10-13
申请号：US12125442
申请日：2008-05-22
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： B03C3/60
CPC分类号： B03C3/41 , B03C3/60 , B03C2201/10 , Y10S977/742
摘要： An air particle precipitator and a method of air filtration include a housing unit; a first conductor in the housing unit; a second conductor in the housing unit; and a carbon nanotube grown on the second conductor. Preferably, the first conductor is positioned opposite to the second conductor. The air particle precipitator further includes an electric field source adapted to apply an electric field to the housing unit. Moreover, the carbon nanotube is adapted to ionize gas in the housing unit, wherein the ionized gas charges gas particulates located in the housing unit, and wherein the first conductor is adapted to trap the charged gas particulates. The air particle precipitator may further include a metal layer over the carbon nanotube.
摘要翻译：空气颗粒除尘器和空气过滤方法包括壳体单元; 住房单元中的第一个导体; 壳体单元中的第二导体; 和在第二导体上生长的碳纳米管。优选地，第一导体与第二导体相对定位。空气粒子除尘器还包括适于向壳体单元施加电场的电场源。此外，碳纳米管适于使壳体单元中的气体电离，其中电离气体对位于壳体单元中的气体微粒进行充电，并且其中第一导体适于捕集带电气体微粒。空气粒子沉淀器还可以包括在碳纳米管上的金属层。

89. 发明授权

US07528494B2 Accessible chip stack and process of manufacturing thereof 有权
标题翻译：无障碍芯片堆栈及其制造工艺
公开(公告)号：US07528494B2
公开(公告)日：2009-05-05
申请号：US11266456
申请日：2005-11-03
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/00 , H01L21/4763
CPC分类号： H01L29/40 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/32145 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002
摘要： A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.
摘要翻译：制造三维集成电路芯片或晶片组件的过程，更具体地说，在将芯片定向成堆叠之前，将其布置在晶片上的处理。还公开了三维集成电路的制造，其中芯片密度可以非常高并且在晶片仍然完整且通常为平面结构的情况下被处理。

90. 发明授权

US07504314B2 Method for fabricating oxygen-implanted silicon on insulation type semiconductor and semiconductor formed therefrom 失效
标题翻译：在绝缘型半导体上形成氧注入硅的方法和由其形成的半导体
公开(公告)号：US07504314B2
公开(公告)日：2009-03-17
申请号：US10907565
申请日：2005-04-06
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Larry A. Nesbit
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Larry A. Nesbit
IPC分类号： H01L29/93 , H01L21/76
CPC分类号： H01L21/76267 , H01L21/76243 , H01L21/76281 , H01L21/76283
摘要： The invention relates generally to a method for fabricating oxygen-implanted semiconductors, and more particularly to a method for fabricating oxygen-implanted silicon-on-insulation (“SOI”) type semiconductors by cutting-up regions into device-sized pieces prior to the SOI-oxidation process. The process sequence to make SOI is modified so that the implant dose may be reduced and relatively long and high temperature annealing process steps may be shortened or eliminated. This simplification may be achieved if, after oxygen implant, the wafer structure is sent to pad formation, and masking and etching. After the etching, annealing or oxidation process steps may be performed to create the SOI wafer.
摘要翻译：本发明一般涉及一种用于制造氧注入半导体的方法，更具体地说，涉及一种用于将氧注入的硅绝缘（“SOI”）型半导体通过切割区域制造成器件尺寸的片之前的方法 SOI氧化工艺。制造SOI的工艺顺序被修改，使得可以减少注入剂量并且相对较长并且可以缩短或消除高温退火工艺步骤。如果在氧注入之后将晶片结构发送到焊盘形成以及掩模和蚀刻，则可以实现这种简化。在蚀刻之后，可以执行退火或氧化工艺步骤以产生SOI晶片。

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