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1. 发明授权

US06614074B2 Grooved planar DRAM transfer device using buried pocket 失效
标题翻译：凹槽平面DRAM传输装置采用埋式口袋
公开(公告)号：US06614074B2
公开(公告)日：2003-09-02
申请号：US09092749
申请日：1998-06-05
申请人： Gary Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , Jack A. Mandelman
发明人： Gary Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , Jack A. Mandelman
IPC分类号： H01L2976
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829
摘要： A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.
摘要翻译：一种带槽的平面DRAM传输装置，其具有形成在位于源极和漏极区域之间的衬底的沟槽中的带槽门。带槽门具有侧壁部分和限定其上的通道的底部部分。底部包括掺杂的凹穴，使得底部上的阈值电压Vt基本上小于侧壁部分上的Vt，使得侧壁部分主要控制通过该装置的电流。

2. 发明授权

US06228705B1 Overlay process for fabricating a semiconductor device 失效
标题翻译：用于制造半导体器件的叠层工艺
公开(公告)号：US06228705B1
公开(公告)日：2001-05-08
申请号：US09243221
申请日：1999-02-03
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , William H. Ma
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , William H. Ma
IPC分类号： H01L218242
CPC分类号： H01L23/544 , H01L27/10861 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A process for fabricating a semiconductor device. In an exemplary embodiment, the process includes the following steps. The process initially defines a first registration mark associated with a first mask level of the semiconductor device and a second registration mark associated with a second mask level of the semiconductor device. The process then defines a third registration mark associated with a third mask level of the semiconductor device based on the first and second registration marks. Finally, the process aligns the third mask level along a first axis with respect to the first registration mark, and aligns the third mask level along a second axis with respect to the second registration mark. According to various aspects of the invention, the semiconductor fabrication process is used to fabricate DRAM trench cells, or any other type of semiconductor device whose fabrication requires tight overlay alignment between the various levels of the device.
摘要翻译：一种制造半导体器件的工艺。在示例性实施例中，该过程包括以下步骤。该过程最初定义与半导体器件的第一掩模级相关联的第一对准标记和与半导体器件的第二掩模级相关联的第二对准标记。然后，该过程基于第一和第二对准标记来定义与半导体器件的第三掩模级相关联的第三对准标记。最后，该过程相对于第一对准标记沿着第一轴对准第三掩模级，并且使第三掩模级别相对于第二对准标记沿着第二轴线对齐。根据本发明的各个方面，半导体制造工艺用于制造DRAM沟槽单元或其制造需要在器件的各个级别之间紧密重叠对准的任何其它类型的半导体器件。

3. 发明授权

US06221680B1 Patterned recess formation using acid diffusion 失效
标题翻译：使用酸扩散形成图形凹陷
公开(公告)号：US06221680B1
公开(公告)日：2001-04-24
申请号：US09127132
申请日：1998-07-31
申请人： Mark C. Hakey , Steven J. Holmes , David Horak , Toshiharu Furukawa
发明人： Mark C. Hakey , Steven J. Holmes , David Horak , Toshiharu Furukawa
IPC分类号： H01L2100
CPC分类号： H01L21/0273 , G03F7/094 , H01L21/02129 , H01L21/02271 , H01L21/312 , H01L21/31625 , H01L27/10861
摘要： The present invention relates to a method for providing patterned recess formation in a previously recessed area of a semiconductor structure, i.e. DRAM trench capacitor, using acid diffusion to selectively activate some, but not all of the acid sensitive material that is filled within the recessed areas of such structures. By employing the method of the present invention, it is possible to recess all the previously recessed areas at the same time providing the same level of recessed acid sensitive material within the previous recessed areas, recess some of the previously recessed areas to a desired level leaving other portions of the structure unrecessed, or recessing the previously recessed areas to contain different levels of the acid sensitive material.
摘要翻译：本发明涉及一种用于在半导体结构（即DRAM沟槽电容器）的预先凹入的区域中提供图案化的凹陷形成的方法，其使用酸扩散来选择性地激活填充在凹陷区域内的一些但不是全部的酸敏感材料的这种结构。通过采用本发明的方法，可以同时在所有先前的凹陷区域内提供相同水平的凹入的酸敏感材料，同时将所有先前凹陷的区域都凹进，将一些先前凹陷的区域凹入到期望的水平位置结构的其他部分不能被加工，或者使先前凹陷的区域凹陷以包含不同水平的酸敏感材料。

4. 发明授权

US06190988B1 Method for a controlled bottle trench for a dram storage node 失效
标题翻译：一种用于剧烈储存节点的受控瓶沟的方法
公开(公告)号：US06190988B1
公开(公告)日：2001-02-20
申请号：US09086174
申请日：1998-05-28
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , William H. Ma , James M. Never
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , William H. Ma , James M. Never
IPC分类号： H01L2120
CPC分类号： H01L27/1087
摘要： A bottle-shaped trench capacitor with a buried plate is formed in a controlled etch process. The bottle-shape is fabricated by etching deep trenches from a layered substrate, using the layers as a mask, and covering the side walls of the substrate with protective oxide and nitride layers. With the side walls covered, deep trench etching is then resumed, and a lower trench portion, below the protective layers of the side wall are formed. By diffusing a first dopant in the lower portion of the deep trench region, using the side wall protective layers as a mask, an etch stop is established for a wet etch process at the p/n junction established by the first dopant. The width of the lower trench portion is regulated by the time and temperature of the diffusion. Removing the doped material and applying a second dopant to the lower trench portion establishes a continuous buried plate region between trenches. A capacitor is formed by applying an insulating layer to the trench and filling with a conductor.
摘要翻译：在受控蚀刻工艺中形成具有掩埋板的瓶形沟槽电容器。通过使用这些层作为掩模蚀刻来自分层衬底的深沟槽，并用保护的氧化物和氮化物层覆盖衬底的侧壁来制造瓶形。在侧壁被覆盖的情况下，然后恢复深沟槽蚀刻，并且形成在侧壁的保护层下方的下沟槽部分。通过在深沟槽区域的下部扩散第一掺杂剂，使用侧壁保护层作为掩模，建立了在由第一掺杂剂建立的p / n结处的湿蚀刻工艺的蚀刻停止。下沟槽部分的宽度由扩散的时间和温度来调节。去除掺杂材料并向下沟槽部分施加第二掺杂剂在沟槽之间建立连续的掩埋板区域。通过向沟槽施加绝缘层并填充导体来形成电容器。

5. 发明授权

US06656807B2 Grooved planar DRAM transfer device using buried pocket 失效
公开(公告)号：US06656807B2
公开(公告)日：2003-12-02
申请号：US09772378
申请日：2001-01-30
申请人： Gary Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , Jack A. Mandelman
发明人： Gary Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David Horak , Jack A. Mandelman
IPC分类号： H01L21336
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829
摘要： A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.

6. 发明授权

US08039334B2 Shared gate for conventional planar device and horizontal CNT 有权
标题翻译：常规平面器件和水平CNT的共用门
公开(公告)号：US08039334B2
公开(公告)日：2011-10-18
申请号：US12902944
申请日：2010-10-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , B01J23/74 , B01J37/0238 , B82Y10/00 , H01L21/7624 , H01L21/823437 , H01L27/286 , H01L51/0048 , H01L51/0545 , H01L51/055 , Y10S977/742 , Y10S977/762 , Y10S977/763
摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
摘要翻译：在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管晶体管位于至少一个平面半导体器件的栅极之上。

7. 发明授权

US08004024B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08004024B2
公开(公告)日：2011-08-23
申请号：US12348404
申请日：2009-01-05
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/423 , H01L29/78
CPC分类号： H01L29/4983 , H01L29/4908 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78621 , Y10S977/742 , Y10S977/847
摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.
摘要翻译：晶体管。晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。

8. 发明授权

US07557023B2 Implantation of gate regions in semiconductor device fabrication 失效
标题翻译：在半导体器件制造中植入栅极区域
公开(公告)号：US07557023B2
公开(公告)日：2009-07-07
申请号：US11532189
申请日：2006-09-15
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L21/425
CPC分类号： H01L29/66545 , H01L21/0273 , H01L21/266 , H01L21/28035 , H01L29/1083 , H01L29/6653 , H01L29/6659
摘要： A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.
摘要翻译：半导体制造方法。该方法包括提供半导体结构，其包括（i）半导体层，（ii）半导体层上的栅极电介质层，以及（iii）栅极电介质层上的栅电极区。栅极电介质层被夹在半导体层和栅极电极区域之间并使其电绝缘。半导体层和栅极介电层共享公共接口表面，其界定垂直于公共接口表面的参考方向并且从半导体层指向栅极介电层。接下来，在栅极电介质层和栅极电极区域上形成抗蚀剂层。接下来，去除在参考方向上正好在栅极区域上方的抗蚀剂层的盖部分，而不去除在参考方向上不在栅电极区域正上方的任何部分的抗蚀剂层。

9. 发明申请

US20090121343A1 CARBON NANOTUBE STRUCTURES FOR ENHANCEMENT OF THERMAL DISSIPATION FROM SEMICONDUCTOR MODULES 有权
标题翻译：用于增强半导体模块散热的碳纳米管结构
公开(公告)号：US20090121343A1
公开(公告)日：2009-05-14
申请号：US11939599
申请日：2007-11-14
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , Charles W. Koburger, III , Krishna V. Singh
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , Charles W. Koburger, III , Krishna V. Singh
IPC分类号： H01L21/50 , H01L23/34
CPC分类号： H01L23/373 , B82Y10/00 , B82Y40/00 , H01L21/6835 , H01L23/3157 , H01L23/433 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/81 , H01L24/94 , H01L29/0657 , H01L2221/6835 , H01L2221/68377 , H01L2224/0401 , H01L2224/05026 , H01L2224/05186 , H01L2224/05561 , H01L2224/05564 , H01L2224/05571 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/10135 , H01L2224/113 , H01L2224/11845 , H01L2224/13021 , H01L2224/13076 , H01L2224/131 , H01L2224/13147 , H01L2224/13184 , H01L2224/13187 , H01L2224/13193 , H01L2224/16221 , H01L2224/1703 , H01L2224/17515 , H01L2224/274 , H01L2224/73253 , H01L2224/81139 , H01L2224/81191 , H01L2224/81193 , H01L2224/81493 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/14 , H01L2924/04953 , H01L2224/05552
摘要： Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.
摘要翻译：公开了在后表面上具有碳纳米管（CNT）的保护簇的改进的半导体晶片结构的实施方案和形成改进的半导体晶片结构的方法。还公开了在后表面上具有暴露的CNT的半导体模块的实施例，用于与散热器一起提供增强的散热以及使用所公开的半导体晶片结构形成半导体模块的方法。

10. 发明申请

US20090087795A1 METHOD AND APPARATUS FOR CLEANING A SEMICONDUCTOR SUBSTRATE IN AN IMMERSION LITHOGRAPHY SYSTEM 失效
标题翻译：用于在浸没层析系统中清洁半导体衬底的方法和装置
公开(公告)号：US20090087795A1
公开(公告)日：2009-04-02
申请号：US12045290
申请日：2008-03-10
申请人： Steven J. Holmes , Mark C. Hakey , Toshiharu Furukawa , David V. Horak
发明人： Steven J. Holmes , Mark C. Hakey , Toshiharu Furukawa , David V. Horak
IPC分类号： G03F7/20
CPC分类号： G03F7/70341 , G03F7/70925
摘要： A method and apparatus for reduction and prevention of residue formation and removal of residues formed in an immersion lithography tool. The apparatus including incorporation of a cleaning mechanism within the immersion head of an immersion lithographic system or including a cleaning mechanism in a cleaning station of an immersion lithographic system.
摘要翻译：一种用于减少和防止残留物形成和去除在浸没式光刻工具中形成的残留物的方法和装置。该设备包括在浸没式光刻系统的浸没头部内并入清洁机构，或者在浸没式光刻系统的清洁站中包括清洁机构。

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