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81. 发明授权

US06549450B1 Method and system for improving the performance on SOI memory arrays in an SRAM architecture system 有权
标题翻译：用于提高SRAM架构系统中SOI存储器阵列性能的方法和系统
公开(公告)号：US06549450B1
公开(公告)日：2003-04-15
申请号：US09708142
申请日：2000-11-08
申请人： Louis L. Hsu , Rajiv V. Joshi , Fariborz Assaderaghi , Mary J. Saccamango
发明人： Louis L. Hsu , Rajiv V. Joshi , Fariborz Assaderaghi , Mary J. Saccamango
IPC分类号： G11C1100
CPC分类号： G11C11/419
摘要： The present invention provides an SOI SRAM architecture system which holds all the bitlines at a lower voltage level, for example, ground, or a fraction of Vdd, during array idle or sleep mode. Preferably, the bitlines are held at a voltage level approximately equal to Vdd minus Vth, where Vth represents the threshold voltage of the transfer devices of the SRAM cells. This prevents the body regions of the transfer devices of each cell of the array from fully charging up, and thus the system avoids the parasitic bipolar leakage current effects attributed to devices fabricated on a partially-depleted SOI substrate. Also, during idle or sleep mode, if all the bitlines are kept at about the Vdd minus Vth voltage level, power consumption by the SRAM architecture system is decreased. This is because the leakage path via one of the transfer gates of all the SRAM cells is greatly minimized. In the SOI SRAM architecture system of the present invention, before the SOI SRAM array is first accessed following the idle or sleep mode, the bitlines are quickly brought up to Vdd. Accordingly, there will not be sufficient time for the SOI body regions of the transfer devices to be charged up. Following access of the array, if the array becomes idle for a period of time, the bitlines are discharged to a lower voltage level again. To realize this, the SOI SRAM architecture system of the present invention includes circuitry for receiving at least one signal indicative of the operating mode of the array and for charging and discharging the array bitlines accordingly.
摘要翻译：本发明提供一种SOI SRAM架构系统，其在阵列空闲或睡眠模式期间将所有位线保持在较低电压电平，例如接地或Vdd的一部分。优选地，位线被保持在大约等于Vdd-Vth的电压电平，其中Vth表示SRAM单元的传送器件的阈值电压。这防止了阵列的每个电池的转移装置的主体区域完全充电，因此系统避免了由部分耗尽的SOI衬底上制造的器件引起的寄生双极泄漏电流效应。而且，在空闲或睡眠模式期间，如果所有位线都保持在Vdd-Vth电压电平左右，则SRAM架构系统的功耗将会降低。这是因为通过所有SRAM单元的传输门之一的泄漏路径被极大地最小化。在本发明的SOI SRAM架构系统中，在空闲或休眠模式之前首先访问SOI SRAM阵列之前，位线被快速地提升到Vdd。因此，传送装置的SOI体区域不会充足的时间。在阵列访问之后，如果阵列空闲一段时间，则位线再次放电到较低的电压电平。为了实现这一点，本发明的SOI SRAM架构系统包括用于接收指示阵列的操作模式的至少一个信号并且相应地对阵列位线进行充电和放电的电路。

82. 发明授权

US06548358B2 Electrically blowable fuse with reduced cross-sectional area 有权
标题翻译：具有减小横截面积的可电熔保险丝
公开(公告)号：US06548358B2
公开(公告)日：2003-04-15
申请号：US09769494
申请日：2001-01-26
申请人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
发明人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
IPC分类号： H01L21336
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.
摘要翻译：半导体保险丝位于用于连接布线的导体之间。保险丝包括位于相邻导体上的间隔物，以及定位在间隔件之间并连接到布线的熔丝元件。导体之间的空间包括包含尽可能小的光刻宽度的第一宽度，并且熔丝元件具有小于第一宽度的第二宽度。

83. 发明授权

US06538932B2 Timing circuit and method for a compilable DRAM 有权
标题翻译：可编程DRAM的定时电路和方法
公开(公告)号：US06538932B2
公开(公告)日：2003-03-25
申请号：US09880598
申请日：2001-06-13
申请人： Wayne F. Ellis , John A. Fifield , Louis L. Hsu
发明人： Wayne F. Ellis , John A. Fifield , Louis L. Hsu
IPC分类号： G11C700
CPC分类号： G11C11/4096 , G11C7/1051 , G11C7/22 , G11C11/4076 , G11C2207/2281
摘要： A semiconductor memory is disclosed, the memory comprising: a memory cell adapted to store a bit; a wordline and a bitline coupled to the memory cell; a primary sense amplifier coupled to the bitline to receive a signal representing the stored bit when the wordline is active; a wordline driver coupled to activate the wordline; and a primary delay device adapted to produce a first delay selected from a range of selectable delays, the primary delay device adapted to compensate for signal propagation delay along the wordline.
摘要翻译：公开了一种半导体存储器，所述存储器包括：适于存储位的存储器单元; 耦合到存储器单元的字线和位线; 当所述字线有效时，耦合到所述位线的初级读出放大器接收表示存储位的信号; 耦合以激活字线的字线驱动器; 以及适于产生从可选延迟的范围中选择的第一延迟的主延迟装置，所述主延迟装置适于补偿沿着字线的信号传播延迟。

84. 发明授权

US06452855B1 DRAM array interchangeable between single-cell and twin-cell array operation 失效
标题翻译： DRAM单元与双电池阵列的操作可互换
公开(公告)号：US06452855B1
公开(公告)日：2002-09-17
申请号：US09755868
申请日：2001-01-05
申请人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
发明人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
IPC分类号： H01L27118
CPC分类号： G11C7/1045 , G11C7/1006 , G11C11/4091 , G11C11/4096 , G11C11/4097
摘要： A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Switching circuitry is included for interchanging between single-cell and twin-cell array operation, and vice versa. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.
摘要翻译：提供能够在用于以单电池或双电池阵列格式存储数据的单电池和双电池阵列操作之间互换的DRAM阵列。优选地，DRAM阵列在一个操作模式期间以单个单元阵列格式操作，并且DRAM阵列在另一个操作模式期间以双电池阵列格式操作。包括开关电路用于单电池和双电池阵列操作之间的互换，反之亦然。还提供了用于将DRAM阵列中存储的数据从单小区转换为双小区阵列格式的方法，反之亦然。

85. 发明授权

US06449202B1 DRAM direct sensing scheme 失效
标题翻译： DRAM直接感测方案
公开(公告)号：US06449202B1
公开(公告)日：2002-09-10
申请号：US09929593
申请日：2001-08-14
申请人： Hiroyuki Akatsu , Louis L. Hsu , Jeremy K. Stephens , Daniel W. Storaska
发明人： Hiroyuki Akatsu , Louis L. Hsu , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： G11C700
CPC分类号： G11C7/062 , G11C11/4091
摘要： A direct sensing circuit and method for reading data from a memory cell connected to a bitline, with open bitline sensing without using a reference bitline signal, onto a data line in a data read operation. Prior to the data read operation, both the bitline and the data line are precharged to precharge voltages and a sense node is precharged to ground. A pFET device has its gate coupled to a signal developed on the bitline from the memory cell to detect and amplify the signal level thereof, and has its source coupled to a voltage source and its drain coupled to a sense node, such that the signal developed on the bitline determines the degree of turn-on of the pFET device. An nFET device has its gate coupled to the sense node to detect and amplify the signal level thereof, and has its drain coupled to the data line. When sensing a low data signal, the signal developed on the bitline causes subthreshold voltage leakage current through the pFET device to charge the gate of the nFET device which is floating to amplify the signal developed on the bitline to pull down the precharged data line. When sensing a high data signal, the pFET device and the nFET device remain inactivated, and the data line remains at its precharge high voltage. An nFET writeback device is coupled between the data line and the bitline which is switched on to begin a data writeback into the memory cell when the signal develops on the data line.
摘要翻译：一种直接感测电路和方法，用于在数据读取操作中在数据线上从连接到位线的存储器单元读取数据，并且将数据线开放位线检测而不使用参考位线信号。在数据读取操作之前，位线和数据线都被预充电到预充电电压，并且感测节点被预充电到地。 pFET器件的栅极耦合到从存储器单元在位线上产生的信号，以检测和放大其信号电平，并且其源极耦合到耦合到感测节点的电压源及其漏极，使得信号发展位线决定了pFET器件导通的程度。 nFET器件的栅极耦合到感测节点以检测和放大其信号电平，并且其漏极耦合到数据线。当感测到低数据信号时，在位线上产生的信号导致通过pFET器件的阈值电压漏电流，以对nFET器件的栅极进行充电，该nFET器件的栅极被浮置以放大在位线上产生的信号，以将预充电的数据线拉下来。当感测高数据信号时，pFET器件和nFET器件保持不激活，并且数据线保持在其预充电高电压。当在数据线上产生信号时，nFET写回装置耦合在数据线和打开的位线之间，以开始对存储器单元的数据写回。

86. 发明授权

US06445626B1 Column redundancy architecture system for an embedded DRAM 失效
标题翻译：用于嵌入式DRAM的列冗余架构系统
公开(公告)号：US06445626B1
公开(公告)日：2002-09-03
申请号：US09821443
申请日：2001-03-29
申请人： Louis L. Hsu , Rajiv V. Joshi , Gregory J. Fredeman
发明人： Louis L. Hsu , Rajiv V. Joshi , Gregory J. Fredeman
IPC分类号： G11C700
CPC分类号： G11C29/848 , G11C29/846 , G11C2207/104
摘要： A column redundancy architecture system for an embedded DRAM (eDRAM) having a wide data bandwidth and wide internal bus width is disclosed which provides column redundancy to defective datalines of the eDRAM. Internally generated column addresses of defective columns of each micro cell block are stored in a memory device during eDRAM array testing. Two redundancy reroute mechanisms are disclosed. The first redundancy reroute mechanism selects at least one defective dataline of the eDRAM and directly replaces the defective dataline(s) with at least one redundancy dataline. The second redundancy reroute mechanism discards the defective dataline column and replaces it with an adjacent dataline column. The dataline columns following the defective dataline column are then replaced with the next adjacent dataline columns including a redundancy dataline column.
摘要翻译：公开了一种具有宽数据带宽和宽内部总线宽度的嵌入式DRAM（eDRAM）的列冗余架构系统，其为eDRAM的缺陷数据库提供列冗余。在eDRAM阵列测试期间，每个微单元块的内部生成的列地址存储在存储器件中。公开了两种冗余重路由机制。第一个冗余重路由机制选择eDRAM的至少一个有缺陷的数据库，并用至少一个冗余数据线直接替换有缺陷的数据库。第二个冗余重路由机制丢弃有缺陷的数据列，并用相邻的数据列替换它。随后，数据线列中的数据栏将被替换为包含冗余数据列的下一个相邻的数据列。

87. 发明授权

US06400619B1 Micro-cell redundancy scheme for high performance eDRAM 有权
标题翻译：用于高性能eDRAM的微单元冗余方案
公开(公告)号：US06400619B1
公开(公告)日：2002-06-04
申请号：US09841950
申请日：2001-04-25
申请人： Louis L. Hsu , Li-Kong Wang
发明人： Louis L. Hsu , Li-Kong Wang
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/24 , G11C2207/104
摘要： A new micro-cell redundancy scheme for a wide bandwidth embedded DRAM having a SRAM cache interface. For each bank of micro-cell array units comprising the eDRAM, at least one micro-cell unit is prepared as the redundancy to replace a defected micro-cell within the bank. After array testing, any defective micro-cell inside the bank is replaced with a redundancy micro-cell for that bank. A fuse bank structure implementing a look-up table is established for recording each redundant micro-cell address and its corresponding repaired micro-cell address. In order to allow simultaneous multi-bank operation, the redundant micro-cells may only replace the defective micro-cells within the same bank. When reading data from eDRAM, or writing data to eDRAM, the micro-cell array address is checked against the look-up table to determine whether that data is to be read from or written to the original micro-cell, or the redundant micro-cell. The micro-cell redundancy scheme is a flexible and reliable method for high-performance eDRAM applications.
摘要翻译：一种用于具有SRAM缓存接口的宽带宽嵌入式DRAM的新型微小区冗余方案。对于包括eDRAM的每个微单元阵列单元组，至少一个微单元单元被准备为冗余以替代该单元内的缺陷微单元。在阵列测试之后，银行内的任何有缺陷的微单元被该银行的冗余微单元替代。建立实现查找表的熔丝库结构，用于记录每个冗余微小区地址及其对应的修复的微小区地址。为了允许同时多行操作，冗余微单元可以仅替换同一个存储体内的有缺陷的微单元。当从eDRAM读取数据或将数据写入eDRAM时，将针对查找表检查微单元阵列地址，以确定该数据是从原始微单元读取还是写入原始微单元，细胞。微单元冗余方案是高性能eDRAM应用的灵活可靠的方法。

88. 发明授权

US06355531B1 Method for fabricating semiconductor devices with different properties using maskless process 失效
标题翻译：使用无掩模工艺制造具有不同特性的半导体器件的方法
公开(公告)号：US06355531B1
公开(公告)日：2002-03-12
申请号：US09634225
申请日：2000-08-09
申请人： Jack A. Mandelman , Louis L. Hsu , Carl J. Radens , William R. Tonti , Li-Kong Wang
发明人： Jack A. Mandelman , Louis L. Hsu , Carl J. Radens , William R. Tonti , Li-Kong Wang
IPC分类号： H01L218236
CPC分类号： H01L21/823892 , H01L21/823807 , H01L21/82385 , Y10S438/981
摘要： A method is provided for fabricating semiconductor devices having different properties on a common semiconductor substrate. The method includes the steps of (a) forming N openings on the semiconductor substrate, wherein each opening is corresponding to a channel region of each semiconductor device, (b) forming oxide layers of an ith type on surfaces of the N openings, (c) depositing gate conductor material of an ith type over structure of the semiconductor devices, the gate conductor material of the ith type having a gate conductor work-function of an ith type, (d) removing the gate conductor material of the ith type such that a predetermined amount of the gate conductor material of the ith type remains in an ith opening to form a gate conductor material layer of the ith type on top surface in the ith opening and the gate conductor material of the ith type deposited in the structure other than the ith opening is removed, (e) removing the oxide layers of the ith type from openings other than the ith opening, (f) repeating the steps of (a) through (e) from “i=1” to “i=N”, and (g) forming at least one layer on surface of each of N gate conductor material layers in the N openings to form a gate conductor, whereby the N semiconductor devices have N gate conductors, respectively, wherein the N gate conductors have N types of gate conductor work-functions. The semiconductor devices also have channel regions of which doping levels are different from each other by implanting the channel regions with different types of implants.
摘要翻译：提供了一种在公共半导体衬底上制造具有不同特性的半导体器件的方法。该方法包括以下步骤：（a）在半导体衬底上形成N个开口，其中每个开口对应于每个半导体器件的沟道区，（b）在N个开口的表面上形成第i个类型的氧化物层，（c ）沉积所述半导体器件的第i型结构的栅极导体材料，所述第i型栅极导体材料具有第i类型的栅极导体功函数，（d）去除所述第i种类型的栅极导体材料，使得第i个类型的栅极导体材料的预定量保持在第i个开口中，以在第i个开口的顶表面上形成第i型的栅极导体材料层，并且沉积在除第除去第i个开口，（e）从第i个开口以外的开口除去第i个类型的氧化物层，（f）重复步骤（a）至（e）从“i = 1”到“i = N “，（g）在其上形成至少一层在N个开口中的N个栅极导体材料层中的每一个的表面形成栅极导体，由此N个半导体器件分别具有N个栅极导体，其中N个栅极导体具有N种类型的栅极导体功函数。半导体器件还具有通过用不同类型的植入物植入沟道区域而使掺杂水平彼此不同的沟道区域。

89. 发明授权

US06341097B1 Selective address space refresh mode 失效
标题翻译：选择性地址空间刷新模式
公开(公告)号：US06341097B1
公开(公告)日：2002-01-22
申请号：US09764654
申请日：2001-01-17
申请人： Louis L. Hsu , Richard Michael Parent , Matthew Robert Wordeman
发明人： Louis L. Hsu , Richard Michael Parent , Matthew Robert Wordeman
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A method and system of refreshing a DRAM having a multitude of successive wordlines. The method comprises the step of starting a refresh cycle, and this starting step includes the steps of (I) counting the wordlines one at a time in succession, (ii) refreshing the wordlines counted over a first period t1, and (iii) at the end of period t1, stopping the refreshing of the wordlines, and continuing the counting of the wordlines for a period t2. The method further comprises the step of, after period t2, restarting the refresh cycle. Preferably, the restarting step includes the steps of, at the end of period t2, delaying for a period t3; and restarting the refresh cycle at the end of period t3. The method may include the further step of adjusting the length of the period t1, and preferably, during the combined periods t1 and t2, all of the wordlines are counted. Also, preferably the processing unit determines the memory space to be refreshed; and, more specifically, this may be accomplished by the processing unit issuing a reset signal to terminate the refresh period t1.
摘要翻译：一种刷新具有多个连续字线的DRAM的方法和系统。该方法包括开始刷新周期的步骤，该开始步骤包括以下步骤：（I）一次一个地对一个字线进行计数，（ii）刷新在第一周期t1计数的字线，以及（iii）时段t1的结束，停止字线的刷新，并且继续对字线计数一段时间t2。该方法还包括在时段t2之后重新启动刷新周期的步骤。优选地，重新开始步骤包括以下步骤：在周期t2结束时，延迟时段t3; 并在周期t3结束时重新启动刷新周期。该方法可以包括调整周期t1的长度的进一步的步骤，优选地，在组合时段t1和t2期间，对所有字线进行计数。此外，优选地，处理单元确定要刷新的存储器空间; 并且更具体地，这可以由处理单元发出复位信号来终止刷新周期t1来实现。

90. 发明授权

US06337595B1 Low-power DC voltage generator system 有权
公开(公告)号：US06337595B1
公开(公告)日：2002-01-08
申请号：US09627599
申请日：2000-07-28
申请人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton , Wayne F. Ellis , Jeffrey H. Dreibelbis
发明人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton , Wayne F. Ellis , Jeffrey H. Dreibelbis
IPC分类号： G05F302
CPC分类号： G05F3/265
摘要： A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt. A one-volt negative voltage pump circuit is also included for pumping the voltages of at least one corresponding charge pump circuit, even when an operating voltage of the DC generator system is at or near one-volt. The DC voltage generator system is specifically designed to be implemented within battery-operated devices having at least one memory unit. The low-power consumption feature of the DC voltage generator system extends battery lifetime and data retention time of the cells of the at least one memory unit.

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