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1. 发明授权

US08495444B2 Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components 失效
公开(公告)号：US08495444B2
公开(公告)日：2013-07-23
申请号：US12163493
申请日：2008-06-27
申请人： Daniel R. Knebel , William Robert Reohr , Li-Kong Wang
发明人： Daniel R. Knebel , William Robert Reohr , Li-Kong Wang
IPC分类号： G01R31/30
CPC分类号： G06F11/008
摘要： A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.

2. 发明授权

US07475320B2 Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components 失效
标题翻译：调整工作频率以补偿老化电子元件的频率修改技术
公开(公告)号：US07475320B2
公开(公告)日：2009-01-06
申请号：US10643549
申请日：2003-08-19
申请人： Daniel R. Knebel , William Robert Reohr , Li-Kong Wang
发明人： Daniel R. Knebel , William Robert Reohr , Li-Kong Wang
IPC分类号： G06F11/32 , G06F11/18
CPC分类号： G06F11/008
摘要： A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.
摘要翻译：在电子系统的特定年龄确定电子系统的许多性能参数。性能参数可以与电子系统的特定年龄的电子系统的电子部件的最大工作频率相关联。电子元件的工作频率根据性能参数进行调整。性能参数可以是预定的（例如通过可靠性和老化测试），在电子系统的寿命期间确定，或者这些的一些组合。性能参数可以包括以前的工作频率，工作时间，环境温度和电源电压。性能参数可以包括使用年龄监测电路确定的性能统计，其中老化电路与仅用于比较的电路进行比较。也可以通过错误检测电路来确定性能统计。如果检测到错误，则可以减少工作频率。

3. 发明授权

US07191371B2 System and method for sequential testing of high speed serial link core 有权
标题翻译：高速串行连接核心序列测试系统及方法
公开(公告)号：US07191371B2
公开(公告)日：2007-03-13
申请号：US10118751
申请日：2002-04-09
申请人： Louis L. Hsu , Li-Kong Wang
发明人： Louis L. Hsu , Li-Kong Wang
IPC分类号： G01R31/28
CPC分类号： H04L1/243
摘要： A testing circuit for testing a series of at least three alternating transmitter and receiver links. The testing circuit including a built-in-self-test (BIST.) macro for generating test data and transmitting the test data to a first link of the series of transmitter and receiver links, and for receiving processed test data from a last link of the series of transmitter receiver links; and at least one test transmission line for transmitting test data received by a link of the series of transmitter and receiver links to a next link of the series of transmitter and receiver links, wherein the at least one test transmission line connects the at least three transmitter and receiver links. A method for testing a series of links having at least three alternating transmitter and receiver links of a plurality of transmitter and receiver links in a SerDes core including generating at least one test data signal; transmitting the at least one test data signal sequentially through the transmitter and receiver links of the series of links; receiving the at least one test data signal from a last link of the series of transmitter and receiver links; and checking the at least one test data signal received.
摘要翻译：用于测试一系列至少三个交替发射机和接收机链路的测试电路。所述测试电路包括用于产生测试数据并将所述测试数据发送到所述一系列发射机和接收机链路的第一链路的内置自测试（BIST）宏，以及从所述一系列发射机和接收机链路的第一链路接收经处理的测试数据一系列发射机接收器链路; 以及至少一个测试传输线，用于将由所述一系列发射机和接收机链路的链路接收的测试数据发射到所述一系列发射机和接收机链路中的下一个链路，其中所述至少一个测试传输线路将所述至少三个发射机和接收器链接。一种用于测试一系列链路的方法，所述链路具有至少三个在SerDes核心中的多个发射机和接收机链路的交替发射机和接收机链路，包括生成至少一个测试数据信号; 通过所述一系列链路的所述发射机和接收机链路顺序地传送所述至少一个测试数据信号; 从所述一系列发射机和接收机链路的最后一个链路接收所述至少一个测试数据信号; 以及检查所接收的至少一个测试数据信号。

4. 发明授权

US07023528B2 Hybrid electronic mask 有权
标题翻译：混合电子面具
公开(公告)号：US07023528B2
公开(公告)日：2006-04-04
申请号：US10167327
申请日：2002-06-10
申请人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： G03B27/72 , G03B27/54 , G03B27/42
CPC分类号： G03F1/26 , G03F7/2014 , G03F7/70291
摘要： An electronically programmable mask for lithography has an array of individually controllable light sources aligned with an array of individually controllable liquid crystals, so that individual pixels may be turned on or off and phase-shifted to provide a desired light intensity distribution on a wafer. The mask may be used in a contact printing mode or in a reduction projection mode.
摘要翻译：用于光刻的电子可编程掩模具有与独立可控液晶阵列对准的独立可控光源的阵列，使得各个像素可以被导通或截止并相移以在晶片上提供期望的光强分布。掩模可以以接触印刷模式或缩小投影模式使用。

5. 发明授权

US06941414B2 High speed embedded DRAM with SRAM-like interface 有权
标题翻译：高速嵌入式DRAM，具有类SRAM接口
公开(公告)号：US06941414B2
公开(公告)日：2005-09-06
申请号：US09855240
申请日：2001-05-15
申请人： Louis L. Hsu , William Wu Shen , Li-Kong Wang
发明人： Louis L. Hsu , William Wu Shen , Li-Kong Wang
IPC分类号： G06F12/08 , G06F13/42 , G11C7/10 , G11C11/4093 , G11C11/4096 , G06F12/00
CPC分类号： G11C7/106 , G06F12/0893 , G06F13/4243 , G06F2212/3042 , G11C7/1006 , G11C7/1012 , G11C7/1039 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C11/4093 , G11C11/4096 , G11C2207/104 , G11C2207/2245
摘要： The invention provides a simple interface circuit between a large capacity, high speed DRAM and a single port SRAM cache to achieve fast-cycle memory performance. The interface circuit provides wider bandwidth internal communications than external data transfers. The interface circuit schedules parallel pipeline operations so that one set of data buses can be shared in cycles by several data flows to save chip area and alleviate data congestion. A flexible design is provided that can be used for a range of bandwidths of data transfer and generally any size bandwidth ranging from 32 to 4096 bits wide can use this same approach.
摘要翻译：本发明提供了在大容量，高速DRAM和单端口SRAM缓存之间的简单接口电路，以实现快速周期的存储器性能。接口电路提供比外部数据传输更宽的带宽内部通信。接口电路调度并行流水线操作，使得一组数据总线可以通过几个数据流循环共享，以节省芯片面积并减轻数据拥塞。提供了灵活的设计，可以用于数据传输的一系列带宽，一般来说，从32到4096位宽的任何大小的带宽可以使用这种相同的方法。

6. 发明授权

US06911354B2 Polymer thin-film transistor with contact etch stops 失效
标题翻译：具有接触蚀刻的聚合物薄膜晶体管停止
公开(公告)号：US06911354B2
公开(公告)日：2005-06-28
申请号：US10681464
申请日：2003-10-08
申请人： Tricia L. Breen , Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Kwong Hon Wong
发明人： Tricia L. Breen , Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L21/00 , H01L29/786 , H01L51/40
CPC分类号： H01L51/057 , H01L51/0021
摘要： A method and structure of forming a vertical polymer transistor structure is disclosed having a first conductive layer, filler structures co-planar with the first conductive layer, a semiconductor body layer above the first conductive layer, a second conductive layer above the semiconductor body layer, and an etch stop strip positioned between a portion of the first conductive layer and the semiconductor body layer.
摘要翻译：公开了形成垂直聚合物晶体管结构的方法和结构，其具有第一导电层，与第一导电层共平面的填充结构，在第一导电层上方的半导体本体层，半导体本体层上方的第二导电层，以及位于第一导电层的一部分和半导体本体层之间的蚀刻停止带。

7. 发明申请

US20050071544A1 Segmented content addressable memory architecture for improved cycle time and reduced power consumption 有权
标题翻译：分段内容可寻址内存架构，可提高周期时间并降低功耗
公开(公告)号：US20050071544A1
公开(公告)日：2005-03-31
申请号：US10673801
申请日：2003-09-29
申请人： Louis Hsu , Brian Ji , Li-Kong Wang
发明人： Louis Hsu , Brian Ji , Li-Kong Wang
IPC分类号： G06F12/00 , G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory (“CAM”) system includes a plurality of segments arranged in an array, wherein each of the plurality of segments includes a plurality of CAM cells, each of the plurality of CAM cells includes a wordline, a matchline and a sinkline, the wordline being shared by all of the cells in the same row, the matchline and sinkline being shared by all of the cells in the same segment; and a corresponding method of searching within a CAM system includes providing an input word to the CAM system, comparing a portion of the input word in a segment of the CAM system, and propagating a mismatch to obviate the need for comparison in other segments of the CAM system.
摘要翻译：内容可寻址存储器（“CAM”）系统包括以阵列排列的多个段，其中多个段中的每个段包括多个CAM单元，多个CAM单元中的每一个包括字线，匹配线和下沉线，该字线由同一行中的所有单元共享，匹配线和汇线由同一段中的所有单元共享; 并且相应的在CAM系统内搜索的方法包括向CAM系统提供输入字，比较CAM系统的片段中的输入字的一部分，并且传播不匹配，以避免在 CAM系统。

8. 发明授权

US06864504B2 Planar polymer transistor 失效
标题翻译：平面聚合物晶体管
公开(公告)号：US06864504B2
公开(公告)日：2005-03-08
申请号：US10453381
申请日：2003-06-03
申请人： Tricia L. Breen , Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Kwong Hon Wong
发明人： Tricia L. Breen , Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L51/05 , H01L21/00 , H01L21/336 , H01L29/786 , H01L35/24 , H01L51/00 , H01L51/40
CPC分类号： H01L51/0001 , H01L51/0024 , H01L51/0516 , H01L51/0541 , H01L51/0545
摘要： A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistor is made with all organic materials. The gate dielectric can be a high-k polymer to boost the device performance. Then, the partially-finished device structures are flipped upside-down and transferred to a second planar carrier. A layer of wax or photo-sensitive organic material is then applied, and can be used as the temporary glue. The device, including its body area, is then defined by an etching process. Contacts to the devices are formed by conductive material deposition and chemical-mechanical polish.
摘要翻译：通过使用第一平面载体来形成包括栅极，源极，漏极和主体元件的器件的第一部分来形成完全平坦化的聚合物薄膜晶体管的结构和方法。优选地，薄膜晶体管由所有有机材料制成。栅极电介质可以是高k聚合物，以提高器件性能。然后，部分完成的装置结构被颠倒翻转并转移到第二平面载体。然后施加一层蜡或光敏有机材料，并且可以用作临时胶。然后通过蚀刻工艺限定该装置，包括其身体区域。与器件的接触通过导电材料沉积和化学机械抛光形成。

9. 发明授权

US06825534B2 Semiconductor device on a combination bulk silicon and silicon-on-insulator (SOI) substrate 有权
标题翻译：组合体硅和绝缘体上硅（SOI）衬底上的半导体器件
公开(公告)号：US06825534B2
公开(公告)日：2004-11-30
申请号：US09748256
申请日：2000-12-27
申请人： Howard H. Chen , Louis L. Hsu , Li-Kong Wang
发明人： Howard H. Chen , Louis L. Hsu , Li-Kong Wang
IPC分类号： H01L2701
CPC分类号： H01L21/76264 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02675 , H01L21/02689 , H01L21/2022 , H01L21/76283 , H01L21/84
摘要： A semiconductor device includes a combination substrate having a bulk silicon region, and a silicon-on-insulator (SOI) region. The SOI region includes a crystallized silicon layer formed by annealing amorphous silicon and having isolation trenches formed therein so as to remove defective regions, and isolation oxides formed in the isolation trenches.
摘要翻译：半导体器件包括具有体硅区域和绝缘体上硅（SOI）区域的组合衬底。 SOI区域包括由非晶硅退火形成的结晶硅层，并且在其中形成有隔离沟槽，以去除不良区域，以及在隔离沟槽中形成隔离氧化物。

10. 发明授权

US06751151B2 Ultra high-speed DDP-SRAM cache 有权
标题翻译：超高速DDP-SRAM缓存
公开(公告)号：US06751151B2
公开(公告)日：2004-06-15
申请号：US09827073
申请日：2001-04-05
申请人： Louis L. Hsu , Toshiaki K. Kirihata , Li-Kong Wang , Robert C. Wong
发明人： Louis L. Hsu , Toshiaki K. Kirihata , Li-Kong Wang , Robert C. Wong
IPC分类号： G11C800
CPC分类号： G06F12/0853 , G11C8/16 , H01L27/1104
摘要： An ultra high-speed DDP-SRAM (Dual Dual-Port Static Random Access Memory) cache having a cache speed in approximately the GHz range. This is accomplished by (1) a specially designed dual-port SRAM whose size is slightly larger than that of a conventional single port SRAM, and (2) the use of a dual dual-port SRAM architecture which doubles its speed by interleaved read and write operations. A first embodiment provides a 6-T (transistor) all nMOS dual-port SRAM cell. A second embodiment provides a dual port 7T-SRAM cell which has only one port for write, and both ports for read.
摘要翻译：具有大约GHz范围内的高速缓存的超高速DDP-SRAM（双重双端口静态随机存取存储器）缓存。这通过（1）专门设计的双端口SRAM（其尺寸略大于常规单端口SRAM）的实现来实现，以及（2）使用双重双端口SRAM架构，其通过交错读取将其速度加倍，写操作。第一实施例提供了6T（晶体管）全部nMOS双端口SRAM单元。第二实施例提供了一个双端口7T-SRAM单元，其仅具有一个用于写入的端口，以及用于读取的两个端口。

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