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1. 发明授权

US06573585B2 Electrically blowable fuse with reduced cross-sectional area 有权
公开(公告)号：US06573585B2
公开(公告)日：2003-06-03
申请号：US09769453
申请日：2001-01-26
申请人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
发明人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
IPC分类号： H01L2900
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

2. 发明授权

US06548358B2 Electrically blowable fuse with reduced cross-sectional area 有权
标题翻译：具有减小横截面积的可电熔保险丝
公开(公告)号：US06548358B2
公开(公告)日：2003-04-15
申请号：US09769494
申请日：2001-01-26
申请人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
发明人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
IPC分类号： H01L21336
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.
摘要翻译：半导体保险丝位于用于连接布线的导体之间。保险丝包括位于相邻导体上的间隔物，以及定位在间隔件之间并连接到布线的熔丝元件。导体之间的空间包括包含尽可能小的光刻宽度的第一宽度，并且熔丝元件具有小于第一宽度的第二宽度。

3. 发明授权

US06222244B1 Electrically blowable fuse with reduced cross-sectional area 失效
标题翻译：具有减小横截面积的可电熔保险丝
公开(公告)号：US06222244B1
公开(公告)日：2001-04-24
申请号：US09093903
申请日：1998-06-08
申请人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
发明人： Kenneth C. Arndt , Dureseti Chidambarrao , Louis L. Hsu , Jack A. Mandelman , Carl Radens
IPC分类号： H01L2900
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.
摘要翻译：半导体保险丝位于用于连接布线的导体之间。保险丝包括位于相邻导体上的间隔物，以及定位在间隔件之间并连接到布线的熔丝元件。导体之间的空间包括包含尽可能小的光刻宽度的第一宽度，并且熔丝元件具有小于第一宽度的第二宽度。

4. 发明申请

US20080283918A1 Ultra Thin Channel (UTC) MOSFET Structure Formed on BOX Regions Having Different Depths and Different Thicknesses Beneath the UTC and SourceDrain Regions and Method of Manufacture Thereof 有权
标题翻译：超薄通道（UTC）MOSFET结构形成在具有不同深度和不同厚度的BOX区域之下，UTC和SourceDrain区域及其制造方法
公开(公告)号：US20080283918A1
公开(公告)日：2008-11-20
申请号：US12166285
申请日：2008-07-01
申请人： Kangguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
发明人： Kangguo Cheng , Dureseti Chidambarrao , Brian Joseph Greene , Jack A. Mandelman , Kern Rim
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/2652 , H01L21/3003 , H01L29/1083 , H01L29/66545 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78603 , H01L29/78621 , H01L29/78696
摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。 UT SOI沟道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。 BOX 1区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。在UT通道区域下面的BOX 2区域的上部与栅极自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于第二个深度。

5. 发明授权

US06777737B2 Vertical DRAM punchthrough stop self-aligned to storage trench 有权
标题翻译：垂直DRAM穿透停止自对准到存储沟槽
公开(公告)号：US06777737B2
公开(公告)日：2004-08-17
申请号：US10016605
申请日：2001-10-30
申请人： Jack A. Mandelman , Dureseti Chidambarrao , Ramachandra Divakaruni
发明人： Jack A. Mandelman , Dureseti Chidambarrao , Ramachandra Divakaruni
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10885 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.
摘要翻译：具有小于约90nm的特征尺寸的显示器很少或没有动态电荷损失并且很少或没有陷阱辅助结漏电的半导体存储器结构被提供。具体地，半导体结构包括存在于含Si衬底中的至少一个背靠背对的沟槽存储存储单元。每个存储单元包括覆盖沟槽电容器的垂直晶体管。在沟槽存储单元的每个垂直侧壁上都存在带外扩散，以将每个存储单元的垂直晶体管和沟槽电容器互连到含Si衬底。穿通阻止掺杂袋位于每个背对背对的沟槽存储存储单元之间，并且其位于相邻存储沟槽的带外扩展之间并且与相邻存储沟槽自对准。

6. 发明授权

US06653678B2 Reduction of polysilicon stress in trench capacitors 失效
标题翻译：减少沟槽电容器中的多晶硅应力
公开(公告)号：US06653678B2
公开(公告)日：2003-11-25
申请号：US09904612
申请日：2001-07-13
申请人： Dureseti Chidambarrao , Rajarao Jammy , Jack A. Mandelman
发明人： Dureseti Chidambarrao , Rajarao Jammy , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/10867
摘要： A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in the DT, recessed below the DT top. The collar is recessed in the DT. A combined poly/counter-recrystallizing species cap is formed over the node electrode with a peripheral strap. The cap may be formed after formed a peripheral divot of a recessed collar, followed by forming an intrinsic poly strap in the divot and doping with a counter-recrystallization species, e.g. Ge, into the node electrode and the strap. Alternatively, the node electrode is recessed followed by codeposition of poly and Ge or another counter-recrystallization species to form the cap and strap.
摘要翻译：半导体衬底中的深沟槽（DT）电容器具有形成在DT底部上方的沟槽侧壁上的隔离环。在轴环下形成一个外板。电容电介质形成在轴环下面的DT壁上。节点电极形成在DT上，凹陷在DT顶部下方。衣领凹入DT。在具有外围带的节点电极上形成组合的聚/反重结晶物质盖。可以在形成凹陷环的外围边缘之后形成盖，然后在该凹陷中形成本征多晶带并掺杂反相再结晶物质，例如， Ge，进入节点电极和带子。或者，节点电极凹进，随后聚合和Ge的共沉积或另一种反重结晶物质形成盖和带。

7. 发明授权

US06534824B1 Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell 失效
标题翻译： 6F2旋转混合DRAM单元的自对准穿通停止
公开(公告)号：US06534824B1
公开(公告)日：2003-03-18
申请号：US10078926
申请日：2002-02-20
申请人： Jack A. Mandelman , Dureseti Chidambarrao
发明人： Jack A. Mandelman , Dureseti Chidambarrao
IPC分类号： H01L2976
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876 , H01L27/10885 , H01L27/10891
摘要： A 6F2 memory cell structure and a method of fabricating the same. The memory cell structure includes a plurality of memory cells located in a Si-containing substrate which are arranged in rows and columns. Each memory cell includes a double-gated vertical MOSFET having exposed gate conductor regions and two gates formed on opposing sidewalls of the MOSFETs. The memory cell structure also includes a plurality of wordlines overlaying the double-gated vertical MOSFETs and in contact with the exposed gate conductor regions, and a plurality of bitlines that are orthogonal to the wordlines. Trench isolation regions are located adjacent to the rows of memory cells. The memory cell structure also includes a plurality of punch through stop regions located in the Si-containing substrate and self-aligned to the wordlines and bitlines. A portion of the punch through stop regions overlap each other under the bitlines and each region serves to electrically isolate adjacent buried-strap regions from each other.
摘要翻译： 6F2存储单元结构及其制造方法。存储单元结构包括位于含Si衬底中的以行和列排列的多个存储单元。每个存储单元包括具有暴露的栅极导体区域和形成在MOSFET的相对侧壁上的两个栅极的双门控垂直MOSFET。存储单元结构还包括覆盖双门控垂直MOSFET并与暴露的栅极导体区域接触的多个字线以及与字线正交的多个位线。沟槽隔离区位于与存储单元行相邻的位置。存储单元结构还包括位于含硅衬底中并与字线和位线自对准的多个穿通停止区域。穿通停止区域的一部分在位线之下彼此重叠，并且每个区域用于将相邻的掩埋区域彼此电隔离。

8. 发明授权

US06833305B2 Vertical DRAM punchthrough stop self-aligned to storage trench 失效
公开(公告)号：US06833305B2
公开(公告)日：2004-12-21
申请号：US10838018
申请日：2004-05-03
申请人： Jack A. Mandelman , Dureseti Chidambarrao , Ramachandra Divakaruni
发明人： Jack A. Mandelman , Dureseti Chidambarrao , Ramachandra Divakaruni
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10885 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.

9. 发明授权

US06740920B2 Vertical MOSFET with horizontally graded channel doping 失效
标题翻译：具有水平梯度通道掺杂的垂直MOSFET
公开(公告)号：US06740920B2
公开(公告)日：2004-05-25
申请号：US10096219
申请日：2002-03-11
申请人： Dureseti Chidambarrao , Kil-Ho Lee , Jack A. Mandelman , Kevin McStay , Rajesh Rengarajan
发明人： Dureseti Chidambarrao , Kil-Ho Lee , Jack A. Mandelman , Kevin McStay , Rajesh Rengarajan
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L21/26586 , H01L27/10838 , H01L29/66666 , H01L29/7827
摘要： Body effects in vertical MOSFET transistors are considerably reduced and other device parameters are unaffected in a vertical transistor having a threshold implant with a peak at the gate and an implant concentration distribution that declines rapidly away from the gate to a plateau having a low p-well concentration value. A preferred embodiment employs two body implants—an angled implant having a peak at the gate that sets the Vt and a laterally uniform low dose implant that sets the well dopant concentration.
摘要翻译：在垂直MOSFET晶体管中的体效应显着降低，并且在具有在栅极处具有峰值的阈值注入的垂直晶体管中的其它器件参数不受影响，并且注入浓度分布从栅极快速下降到具有低p阱的平台浓度值。优选实施例采用两个体植入物 - 成角度的植入物，其在浇口处具有设置Vt的峰值，以及设置阱掺杂剂浓度的横向均匀的低剂量注入。

10. 发明授权

US06872620B2 Trench capacitors with reduced polysilicon stress 失效
标题翻译：减少多晶硅应力的沟槽电容器
公开(公告)号：US06872620B2
公开(公告)日：2005-03-29
申请号：US10441887
申请日：2003-05-20
申请人： Dureseti Chidambarrao , Rajarao Jammy , Jack A. Mandelman
发明人： Dureseti Chidambarrao , Rajarao Jammy , Jack A. Mandelman
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10867
摘要： A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in the DT, recessed below the DT top. The collar is recessed in the DT. A combined poly/counter-recrystallizing species cap is formed over the node electrode with a peripheral strap. The cap may be formed after formed a peripheral divot of a recessed collar, followed by forming an intrinsic poly strap in the divot and doping with a counter-recrystallization species, e.g. Ge, into the node electrode and the strap. Alternatively, the node electrode is recessed followed by codeposition of poly and Ge or another counter-recrystallization species to form the cap and strap.
摘要翻译：半导体衬底中的深沟槽（DT）电容器具有形成在DT底部上方的沟槽侧壁上的隔离环。在轴环下形成一个外板。电容电介质形成在轴环下面的DT壁上。节点电极形成在DT上，凹陷在DT顶部下方。衣领凹入DT。在具有外围带的节点电极上形成组合的聚/反重结晶物质盖。可以在形成凹陷环的外围边缘之后形成盖，然后在该凹陷中形成本征多晶带并掺杂反相再结晶物质，例如， Ge，进入节点电极和带子。或者，节点电极凹进，随后聚合和Ge的共沉积或另一种反重结晶物质形成盖和带。

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