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1. 发明授权

US06337595B1 Low-power DC voltage generator system 有权
公开(公告)号：US06337595B1
公开(公告)日：2002-01-08
申请号：US09627599
申请日：2000-07-28
申请人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton , Wayne F. Ellis , Jeffrey H. Dreibelbis
发明人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton , Wayne F. Ellis , Jeffrey H. Dreibelbis
IPC分类号： G05F302
CPC分类号： G05F3/265
摘要： A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt. A one-volt negative voltage pump circuit is also included for pumping the voltages of at least one corresponding charge pump circuit, even when an operating voltage of the DC generator system is at or near one-volt. The DC voltage generator system is specifically designed to be implemented within battery-operated devices having at least one memory unit. The low-power consumption feature of the DC voltage generator system extends battery lifetime and data retention time of the cells of the at least one memory unit.

2. 发明授权

US06507237B2 Low-power DC voltage generator system 失效
公开(公告)号：US06507237B2
公开(公告)日：2003-01-14
申请号：US10039874
申请日：2002-01-03
申请人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton , Wayne F. Ellis , Jeffrey H. Dreibelbis
发明人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton , Wayne F. Ellis , Jeffrey H. Dreibelbis
IPC分类号： G05F110
CPC分类号： G05F3/265
摘要： A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt. A one-volt negative voltage pump circuit is also included for pumping the voltages of at least one corresponding charge pump circuit, even when an operating voltage of the DC generator system is at or near one-volt. The DC voltage generator system is specifically designed to be implemented within battery-operated devices having at least one memory unit. The low-power consumption feature of the DC voltage generator system extends battery lifetime and data retention time of the cells of the at least one memory unit.

3. 发明授权

US07305515B2 Performance optimizing compiler for building a compiled DRAM 失效
标题翻译：用于构建编译的DRAM的性能优化编译器
公开(公告)号：US07305515B2
公开(公告)日：2007-12-04
申请号：US09793037
申请日：2001-02-26
申请人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
发明人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F17/5045
摘要： A compiler is provided for compiling at least one array or bank unit of a DRAM macro such that electrical performance, including cycle time, access time, setup time, among other properties, is optimized. The compiler compiles the DRAM macro according to inputted information. The compiler receives an input capacity and configuration for the DRAM macro. A compiler algorithm determines a number of wordlines and bitlines required to create the DRAM macro of the input capacity. The compiler algorithm optimizes the cycle time and access time of the DRAM macro by properly configuring a support unit of the DRAM macro based upon the number of wordlines and bitlines.
摘要翻译：提供了一种用于编译DRAM宏的至少一个阵列或存储体单元的编译器，使得包括循环时间，访问时间，建立时间在内的电性能以及其他特性被优化。编译器根据输入的信息编译DRAM宏。编译器接收DRAM宏的输入容量和配置。编译器算法确定创建输入容量的DRAM宏所需的字数和位线数。编译器算法通过根据字线和位线的数量正确配置DRAM宏的支持单元来优化DRAM宏的周期时间和访问时间。

4. 发明授权

US06452855B1 DRAM array interchangeable between single-cell and twin-cell array operation 失效
标题翻译： DRAM单元与双电池阵列的操作可互换
公开(公告)号：US06452855B1
公开(公告)日：2002-09-17
申请号：US09755868
申请日：2001-01-05
申请人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
发明人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
IPC分类号： H01L27118
CPC分类号： G11C7/1045 , G11C7/1006 , G11C11/4091 , G11C11/4096 , G11C11/4097
摘要： A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Switching circuitry is included for interchanging between single-cell and twin-cell array operation, and vice versa. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.
摘要翻译：提供能够在用于以单电池或双电池阵列格式存储数据的单电池和双电池阵列操作之间互换的DRAM阵列。优选地，DRAM阵列在一个操作模式期间以单个单元阵列格式操作，并且DRAM阵列在另一个操作模式期间以双电池阵列格式操作。包括开关电路用于单电池和双电池阵列操作之间的互换，反之亦然。还提供了用于将DRAM阵列中存储的数据从单小区转换为双小区阵列格式的方法，反之亦然。

5. 发明授权

US06233184B1 Structures for wafer level test and burn-in 失效
标题翻译：晶圆级测试和老化的结构
公开(公告)号：US06233184B1
公开(公告)日：2001-05-15
申请号：US09191954
申请日：1998-11-13
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译：晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

6. 发明授权

US06426904B2 Structures for wafer level test and burn-in 失效
标题翻译：晶圆级测试和老化的结构
公开(公告)号：US06426904B2
公开(公告)日：2002-07-30
申请号：US09803500
申请日：2001-03-09
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译：晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低了老化所需的时间。沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

7. 发明授权

US5463335A Power up detection circuits 失效
标题翻译：上电检测电路
公开(公告)号：US5463335A
公开(公告)日：1995-10-31
申请号：US969594
申请日：1992-10-30
申请人： Sridhar Divakaruni , Jeffrey H. Dreibelbis , Wayne F. Ellis , Anatol Furman , Howard L. Kalter
发明人： Sridhar Divakaruni , Jeffrey H. Dreibelbis , Wayne F. Ellis , Anatol Furman , Howard L. Kalter
IPC分类号： H01L27/00 , H03K17/22
CPC分类号： H03K17/223
摘要： A power up detection circuit is provided which includes a power supply terminal, an output terminal, an impedance device coupling the output terminal to the power supply terminal and a latch including a first inverter having a first device connected between the output terminal and a point of reference potential and a second device connected between the output terminal and the power supply terminal, the devices are designed so that subthreshold current passing through the first device is greater than the effective subthreshold current passing through the impedance device and the second device, and a second inverter including third and fourth devices which are designed so that a smaller subthreshold current passes through the third device than the subthreshold current passing through the fourth device. The power up circuit may further include a capacitor connected between the power supply terminal and gate electrodes of the first and second devices.
摘要翻译：提供了一种上电检测电路，其包括电源端子，输出端子，将输出端子耦合到电源端子的阻抗装置和包括第一反相器的锁存器，第一反相器具有连接在输出端子与点参考电位和连接在输出端子和电源端子之间的第二器件，器件被设计成使得通过第一器件的亚阈值电流大于通过阻抗器件和第二器件的有效亚阈值电流，并且第二器件逆变器包括第三和第四器件，其被设计为使得比通过第四器件的亚阈值电流更小的亚阈值电流通过第三器件。上电电路还可以包括连接在第一和第二器件的电源端子和栅电极之间的电容器。

8. 发明授权

US06580650B2 DRAM word line voltage control to insure full cell writeback level 有权
标题翻译： DRAM字线电压控制，以确保全单元回写级别
公开(公告)号：US06580650B2
公开(公告)日：2003-06-17
申请号：US09810325
申请日：2001-03-16
申请人： Wayne F. Ellis , Russell J. Houghton , Mark D. Jacunski , Thomas M. Maffitt , William R. Tonti
发明人： Wayne F. Ellis , Russell J. Houghton , Mark D. Jacunski , Thomas M. Maffitt , William R. Tonti
IPC分类号： G11C700
CPC分类号： G11C11/4085 , G11C8/08
摘要： A DC analog circuit which monitors a DRAM sample cell access device and outputs a DC reference voltage to the word line voltage regulation system. The resulting output voltage Vpp from the word line voltage regulation system will then vary in accordance with the cell access device parametrics so as to guarantee a full high level will always be written into the DRAM cell.
摘要翻译： DC模拟电路，用于监视DRAM采样单元存取装置，并将直流参考电压输出到字线电压调节系统。然后，来自字线电压调节系统的结果输出电压Vpp将根据信元接入设备参数而变化，以保证将始终向DRAM单元写入一个完整的高电平。

9. 发明授权

US6121106A Method for forming an integrated trench capacitor 失效
标题翻译：用于形成集成沟槽电容器的方法
公开(公告)号：US6121106A
公开(公告)日：2000-09-19
申请号：US38395
申请日：1998-03-11
申请人： Wayne F. Ellis , Russell J. Houghton , Max G. Levy , William R. Tonti
发明人： Wayne F. Ellis , Russell J. Houghton , Max G. Levy , William R. Tonti
IPC分类号： H01L21/334 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10894 , H01L29/66181
摘要： A shallow trench capacitor is disclosed that is fabricated by forming a shallow trench in a substrate extending below a surface of the substrate. A dielectric layer having a preselected thickness is grown in the shallow trench, and a polysilicon layer is deposited over the dielectric layer. The polysilicon layer is then planarized down to the nitride or pad layer forming a capacitor. By utilizing a non-critical mask to open up selected regions, isolation structures may then be formed through shallow trench technology.
摘要翻译：公开了一种浅沟槽电容器，其通过在衬底的表面下方延伸的衬底中形成浅沟槽来制造。在浅沟槽中生长具有预选厚度的电介质层，并且在电介质层上沉积多晶硅层。然后将多晶硅层平坦化成形成电容器的氮化物或焊盘层。通过利用非关键掩模来打开所选择的区域，然后可以通过浅沟槽技术形成隔离结构。

10. 发明授权

US06252806B1 Multi-generator, partial array Vt tracking system to improve array retention time 失效
标题翻译：多发生器，部分阵列Vt跟踪系统，提高阵列保留时间
公开(公告)号：US06252806B1
公开(公告)日：2001-06-26
申请号：US09579749
申请日：2000-05-26
申请人： Wayne F. Ellis , Louis L. Hsu , Brian L. Ji , Yujon Li , Oliver Weinfurtner
发明人： Wayne F. Ellis , Louis L. Hsu , Brian L. Ji , Yujon Li , Oliver Weinfurtner
IPC分类号： G11C1604
CPC分类号： G11C8/08 , G11C5/146 , G11C5/147 , G11C11/4074 , G11C11/4078 , G11C2207/104
摘要： Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.
摘要翻译：通过使用以一小部分监视晶体管阈值电压跟踪的偏置电压调节来获得改进的晶体管阵列器件性能。电路和方法对于改善诸如DRAM和嵌入式DRAM的晶体管阵列器件的性能特别有用。这些优点是特别是当通过至少一个监视晶体管的实际阈值电压的一部分进行跟踪来调节通常提供给阵列的至少两个偏置电压时。性能改进包括改进的可靠性，更宽的操作偏置条件，降低的功耗以及（在存储器单元的情况下）改进的保留时间。

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