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1. 发明授权

US07774660B2 Flexible row redundancy system 失效
标题翻译：灵活的行冗余系统
公开(公告)号：US07774660B2
公开(公告)日：2010-08-10
申请号：US12131307
申请日：2008-06-02
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。

2. 发明授权

US06445626B1 Column redundancy architecture system for an embedded DRAM 失效
标题翻译：用于嵌入式DRAM的列冗余架构系统
公开(公告)号：US06445626B1
公开(公告)日：2002-09-03
申请号：US09821443
申请日：2001-03-29
申请人： Louis L. Hsu , Rajiv V. Joshi , Gregory J. Fredeman
发明人： Louis L. Hsu , Rajiv V. Joshi , Gregory J. Fredeman
IPC分类号： G11C700
CPC分类号： G11C29/848 , G11C29/846 , G11C2207/104
摘要： A column redundancy architecture system for an embedded DRAM (eDRAM) having a wide data bandwidth and wide internal bus width is disclosed which provides column redundancy to defective datalines of the eDRAM. Internally generated column addresses of defective columns of each micro cell block are stored in a memory device during eDRAM array testing. Two redundancy reroute mechanisms are disclosed. The first redundancy reroute mechanism selects at least one defective dataline of the eDRAM and directly replaces the defective dataline(s) with at least one redundancy dataline. The second redundancy reroute mechanism discards the defective dataline column and replaces it with an adjacent dataline column. The dataline columns following the defective dataline column are then replaced with the next adjacent dataline columns including a redundancy dataline column.
摘要翻译：公开了一种具有宽数据带宽和宽内部总线宽度的嵌入式DRAM（eDRAM）的列冗余架构系统，其为eDRAM的缺陷数据库提供列冗余。在eDRAM阵列测试期间，每个微单元块的内部生成的列地址存储在存储器件中。公开了两种冗余重路由机制。第一个冗余重路由机制选择eDRAM的至少一个有缺陷的数据库，并用至少一个冗余数据线直接替换有缺陷的数据库。第二个冗余重路由机制丢弃有缺陷的数据列，并用相邻的数据列替换它。随后，数据线列中的数据栏将被替换为包含冗余数据列的下一个相邻的数据列。

3. 发明申请

US20080229144A1 FLEXIBLE ROW REDUNDANCY SYSTEM 失效
标题翻译：灵活的冗余系统
公开(公告)号：US20080229144A1
公开(公告)日：2008-09-18
申请号：US12131307
申请日：2008-06-02
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G06F11/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。

4. 发明授权

US07404113B2 Flexible row redundancy system 有权
标题翻译：灵活的行冗余系统
公开(公告)号：US07404113B2
公开(公告)日：2008-07-22
申请号：US11031138
申请日：2005-01-07
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 复制逻辑模块被编程为根据可选择的修复字段大小将至少一个故障地址复制到存储在对应于预定数量的存储体的行熔丝阵列中的行熔丝信息中。

5. 发明授权

US07093171B2 Flexible row redundancy system 失效
标题翻译：灵活的行冗余系统
公开(公告)号：US07093171B2
公开(公告)日：2006-08-15
申请号：US10115348
申请日：2002-04-03
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 复制逻辑模块被编程为根据可选择的修复字段大小将至少一个故障地址复制到存储在对应于预定数量的存储体的行熔丝阵列中的行熔丝信息中。

6. 发明授权

US07994042B2 Techniques for impeding reverse engineering 有权
标题翻译：阻止逆向工程的技术
公开(公告)号：US07994042B2
公开(公告)日：2011-08-09
申请号：US11924735
申请日：2007-10-26
申请人： Louis L. Hsu , Rajiv V. Joshi , David W. Kruger
发明人： Louis L. Hsu , Rajiv V. Joshi , David W. Kruger
IPC分类号： H01L21/00
CPC分类号： H01L21/76816 , H01L21/76825 , H01L21/76831 , H01L21/76834 , H01L23/573 , H01L27/02 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.
摘要翻译：提供了反逆向工程技术。一方面，提供了一种在绝缘层中形成至少一个特征的方法。该方法包括以下步骤。离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同在植入区域外侧。空隙填充有至少一种导体材料以在绝缘层中形成特征。

7. 发明授权

US06683805B2 Suppression of leakage currents in VLSI logic and memory circuits 有权
标题翻译： VLSI逻辑和存储器电路中泄漏电流的抑制
公开(公告)号：US06683805B2
公开(公告)日：2004-01-27
申请号：US10067411
申请日：2002-02-05
申请人： Rajiv V. Joshi , Louis L. Hsu , Azeez J. Bhavnagarwala
发明人： Rajiv V. Joshi , Louis L. Hsu , Azeez J. Bhavnagarwala
IPC分类号： G11C11413
CPC分类号： G11C11/412
摘要： An SRAM system is provided having an array of SRAM cells including at least one circuit receiving a first power voltage and a power control circuit for supplying a second power voltage to at least one selected circuit of the at least one circuit. The system is one of a memory array and a logic system, and a circuit of the at least one circuit is one of a memory cell of the memory array, a sense amplifier of the memory array and a path of the logic system. A method is also provided for providing a power supply voltage to at least one circuit of a system.
摘要翻译：提供一种SRAM系统，其具有包括至少一个接收第一电源电压的电池的SRAM单元阵列和用于向至少一个电路的至少一个选定电路提供第二电源电压的功率控制电路。该系统是存储器阵列和逻辑系统之一，并且至少一个电路的电路是存储器阵列的存储单元，存储器阵列的读出放大器和逻辑系统的路径之一。还提供了一种用于向系统的至少一个电路提供电源电压的方法。

8. 发明授权

US06617702B2 Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate 有权
标题翻译：半导体器件利用对准标记来全面对准半导体衬底的正面和背面
公开(公告)号：US06617702B2
公开(公告)日：2003-09-09
申请号：US09769080
申请日：2001-01-25
申请人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , Tsorng-Dih Yuan
发明人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , Tsorng-Dih Yuan
IPC分类号： H01L23544
CPC分类号： H01L23/48 , H01L21/8221 , H01L23/544 , H01L24/48 , H01L24/73 , H01L27/0694 , H01L2223/54473 , H01L2224/05599 , H01L2224/16225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2224/85399 , H01L2924/00014 , H01L2924/01039 , H01L2924/01077 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , Y10T29/49133 , Y10T29/49155 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one or more substrates. In one embodiment, two circuit systems situated on opposite sides of a substrate are aligned to provide for wireless communications between the two circuit systems through the substrate. In another embodiment, communication devices situated on one or more substrates are aligned to provide for wireless communications between the communication devices through the one or more substrates. In another embodiment, two chips situated on opposite sides of a transparent substrate are aligned to provide for wireless communications between the two chips through the transparent substrate.
摘要翻译：本发明提供了在一个或多个基板的正面和背面上制造或结合到其上的微电子电路系统，例如通信设备和芯片，以提供通过一个或多个基板的电路系统之间的无线通信。在一个实施例中，位于衬底的相对侧上的两个电路系统被对准以提供通过衬底的两个电路系统之间的无线通信。在另一个实施例中，位于一个或多个基板上的通信设备被对准以通过一个或多个基板来提供通信设备之间的无线通信。在另一个实施例中，位于透明基板的相对侧上的两个芯片被对准以提供通过透明基板的两个芯片之间的无线通信。

9. 发明授权

US5426330A Refractory metal capped low resistivity metal conductor lines and vias 失效
$Refractory metal capped low resistivity metal conductor lines and vias$
标题翻译：耐火金属封盖的低电阻金属导线和通孔
公开(公告)号：US5426330A
公开(公告)日：1995-06-20
申请号：US125107
申请日：1993-09-21
申请人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
发明人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
IPC分类号： H01L21/28 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/7684 , H01L21/76847 , H01L21/76849 , H01L21/76852 , H01L21/76877 , H01L23/49866 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/09701 , Y10S148/015 , Y10S257/915 , Y10S438/959
摘要： A device includes a substrate, at least one dielectric layer positioned on said substrate, and metalization positioned in an opening in the at least one dielectric layer and extending a predetermined distance towards the substrate from a surface which is substantially coplanar with a surface of the at least one dielectric layer. The metalization includes a low resistivity metal or alloy encapsulated by a refractory metal or alloy having a resistivity greater than that of the low resistivity metal or alloy and having a columnar structure. The metalization has a plurality of sides in cross-section, at least three sides of the plurality of sides being substantially formed of a refractory metal or alloy having a common composition, at least two sides of the plurality of sides extending substantially the predetermined distance, and all of the plurality of sides being formed within the opening in the at least one dielectric layer.
摘要翻译：一种器件包括衬底，位于所述衬底上的至少一个电介质层和位于所述至少一个介电层中的开口中的金属化，并且从与所述衬底的表面基本上共面的表面向所述衬底延伸预定距离至少一个介电层。金属化包括由难熔金属或合金包覆的低电阻率金属或合金，其电阻率大于低电阻率金属或合金的电阻率，并具有柱状结构。金属化具有多个横截面，多个侧面的至少三个边基本上由具有共同成分的难熔金属或合金形成，多个侧面的至少两侧基本上延伸预定距离，并且所述多个侧面中的所有多个侧面形成在所述至少一个介电层中的开口内。

10. 发明授权

US5300813A Refractory metal capped low resistivity metal conductor lines and vias 失效
$Refractory metal capped low resistivity metal conductor lines and vias$
标题翻译：耐火金属封盖的低电阻金属导线和通孔
公开(公告)号：US5300813A
公开(公告)日：1994-04-05
申请号：US841967
申请日：1992-02-26
申请人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
发明人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
IPC分类号： H01L21/28 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532 , H01L29/440 , H01L29/460
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/7684 , H01L21/76847 , H01L21/76849 , H01L21/76852 , H01L21/76877 , H01L23/49866 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/09701 , Y10S148/015 , Y10S257/915 , Y10S438/959
摘要： A contact structure for a semiconductor device having a first refractory metal layer formed only at the bottom of a contact hole. The first refractory metal is selected from a group comprising titanium (Ti), titanium alloys or compounds such as Ti/TiN, tungsten (W), titanium/tungsten (Ti/W) alloys, or chromium (Cr) or tantalum (Ta) and their alloys or some other suitable material. A low resistivity layer comprising a single, binary or ternary metalization is deposited over the first refractory metal layer in the contact hole by a method such as PVD using evaporation or collimated sputtering. The low resistivity layer has side walls which taper inwardly toward one another with increasing height of the layer and the low resistivity layer does not contact the side walls of the contact hole. The low resistivity layer may be Al.sub.x Cu.sub.y (x+y=1; x.gtoreq.0, y.gtoreq.0), ternary alloys such as Al-Pd-Cu or multicomponent alloys such as Al-Pd-Nb-Au. A second refractory metal layer is deposited over the low resistivity layer. The second refractory metal layer may be tungsten, cobalt, nickel, molybdenum or alloys/compounds such as Ti/TiN. The first and second refractory metal layers completely encapsulate the low resistivity layer. The first and second refractory metal layers can comprise an alloy containing silicon with a higher incorporated silicon content near the top of the contact hold present as a distinct or graded composition than at a location closer to the bottom of the contact hole.
摘要翻译：一种用于半导体器件的接触结构，其具有仅在接触孔的底部形成的第一难熔金属层。第一难熔金属选自钛（Ti），钛合金或Ti / TiN，钨（W），钛/钨（Ti / W）合金或铬（Cr）或钽（Ta）及其合金或其他合适的材料。包含单一二元或三元金属化的低电阻率层通过诸如使用蒸发或准直溅射的PVD的方法沉积在接触孔中的第一难熔金属层上。低电阻率层具有随着层的高度逐渐向内逐渐向内逐渐变细的侧壁，低电阻层不接触接触孔的侧壁。低电阻率层可以是AlxCuy（x + y = 1; x> = 0，y> = 0），诸如Al-Pd-Cu的三元合金或诸如Al-Pd-Nb-Au的多组分合金。在低电阻率层上沉积第二难熔金属层。第二耐火金属层可以是钨，钴，镍，钼或诸如Ti / TiN的合金/化合物。第一和第二难熔金属层完全封装低电阻率层。第一和第二难熔金属层可以包含含有硅的合金，其中接合保持层的顶部附近具有更高的掺入硅含量，作为不同或分级的组成，而不是靠近接触孔底部的位置。

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