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71. 发明申请

US20060101104A1 Optimizing layout of an application on a massively parallel supercomputer 失效
标题翻译：在大型并行超级计算机上优化应用程序的布局
公开(公告)号：US20060101104A1
公开(公告)日：2006-05-11
申请号：US10963101
申请日：2004-10-12
申请人： Gyan Bhanot , Alan Gara , Philip Heidelberger , Eoin Lawless , James Sexton , Robert Walkup
发明人： Gyan Bhanot , Alan Gara , Philip Heidelberger , Eoin Lawless , James Sexton , Robert Walkup
IPC分类号： G06F1/16
CPC分类号： G06F9/5066
摘要： A general computer-implement method and apparatus to optimize problem layout on a massively parallel supercomputer is described. The method takes as input the communication matrix of an arbitrary problem in the form of an array whose entries C(i, j) are the amount to data communicated from domain i to domain j. Given C(i, j), first implement a heuristic map is implemented which attempts sequentially to map a domain and its communications neighbors either to the same supercomputer node or to near-neighbor nodes on the supercomputer torus while keeping the number of domains mapped to a supercomputer node constant (as much as possible). Next a Markov Chain of maps is generated from the initial map using Monte Carlo simulation with Free Energy (cost function) F=Σi,jC(i,j)H(i,j)—where H(i,j) is the smallest number of hops on the supercomputer torus between domain i and domain j. On the cases tested, found was that the method produces good mappings and has the potential to be used as a general layout optimization tool for parallel codes. At the moment, the serial code implemented to test the method is un-optimized so that computation time to find the optimum map can be several hours on a typical PC. For production implementation, good parallel code for our algorithm would be required which could itself be implemented on supercomputer.
摘要翻译：描述了在大型并行超级计算机上优化问题布局的通用计算机实现方法和装置。该方法采用数组形式的任意问题的通信矩阵作为输入，其条目C（i，j）是从域i到域j传送的数据量。给定C（i，j），首先实现启发式映射，其尝试顺序地将域及其通信邻居映射到超级计算机节点或超级计算机环面上的近邻节点，同时保持域的数量映射到超级计算机节点常数（尽可能多）。接下来，使用具有自由能量（成本函数）的蒙特卡罗模拟，从初始映射生成马尔可夫链映射，其中F =Σi，j C（i，j）H（i，j） H（i，j）是域i和域j之间的超级计算机环面上的最小跳数。在测试的情况下，发现该方法产生良好的映射，并且有可能被用作并行代码的通用布局优化工具。此时，实现测试方法的序列号未优化，以便在典型的PC上找到最佳映射的计算时间可以为几个小时。对于生产实现，将需要我们的算法的良好的并行代码，这本身可以在超级计算机上实现。

72. 发明授权

US07039769B2 Direct addressed shared compressed memory system 失效
公开(公告)号：US07039769B2
公开(公告)日：2006-05-02
申请号：US10158534
申请日：2002-05-30
申请人： Vittorio Castelli , Peter A. Franaszek , Philip Heidelberger , John Timothy Robinson
发明人： Vittorio Castelli , Peter A. Franaszek , Philip Heidelberger , John Timothy Robinson
IPC分类号： G06F12/06
CPC分类号： G06F12/0284 , G06F12/08 , G06F12/10 , G06F12/1458 , G06F2212/401
摘要： In a computer system in which a plurality of hosts is connected through an interconnection network, an apparatus coupled to the interconnection network for allowing the plurality of hosts to share a collection of memory sectors, the memory sectors storing compressed data, is provided. The apparatus includes a network adapter for coupling the apparatus to the interconnection network; a memory for storing the collection of memory sectors; and control logic for managing the memory, the control logic including a memory compressor/decompressor. The memory further includes a directory for translating real addresses of at least one host to an address in the apparatus. A method for managing a number of memory sectors used by each host and a method for translating a real address specified by at least one host into a real address of the apparatus is also provided.

73. 发明授权

US07024512B1 Compression store free-space management 失效
标题翻译：压缩店自由空间管理
公开(公告)号：US07024512B1
公开(公告)日：2006-04-04
申请号：US09021333
申请日：1998-02-10
申请人： Peter Anthony Franaszek , Philip Heidelberger
发明人： Peter Anthony Franaszek , Philip Heidelberger
IPC分类号： G06F12/00 , G06F9/00
CPC分类号： G06F12/023 , G06F12/08 , G06F2212/401 , Y10S707/99942
摘要： An improved method, system, and a computer program storage device (e.g., including software embodied on a magnetic, electrical, optical, or other storage device) for management of compressed main memory allocation and utilization which can avoid system abends or inefficient operation that would otherwise result. One feature reduces (and ultimately eliminates) all unessential processing as the amount of available storage decreases to a point low enough to threaten a system abend. In another example, the amount of current memory usage is determined as well as one or more of: an estimate of an amount of allocated but unused memory; a determination of the amount of memory required for outstanding I/O requests. The compressed memory is managed as a function of the current memory usage and one or more of the other measured or estimated quantities. The compressed memory can be managed by maintaining a set of dynamic thresholds; estimating the amount of storage that can easily be freed (used but available) and the amount of storage that is committed (allocated but unused). The estimate of committed storage can include: the current storage utilization; and an estimate of storage committed to new pages (based on the number of new pages granted), the times at which this was done, the estimated compression ratio, and estimates of residency times in the cache.
摘要翻译：改进的方法，系统和计算机程序存储设备（例如，包括在磁性，电气，光学或其他存储设备上实现的软件），用于管理压缩的主存储器分配和利用，其可以避免系统退出或低效的操作，否则结果。一个功能减少（并最终消除）所有不必要的处理，因为可用存储空间的数量减少到足以威胁系统退出的程度。在另一示例中，确定当前存储器使用量，以及以下中的一个或多个：已分配但未使用的存储器的量的估计; 确定未完成的I / O请求所需的内存量。根据当前内存使用情况和一个或多个其他测量或估计的数量来管理压缩存储器。可以通过维护一组动态阈值来管理压缩存储器; 估计可以轻松释放（已用但可用）的存储量和已提交（已分配但未使用）的存储量。承诺存储的估计可以包括：当前的存储利用率; 以及对新页面的存储量的估计（基于授予的新页面数量），完成的时间，估计的压缩率以及高速缓存中的驻留时间的估计。

74. 发明授权

US06381586B1 Pricing of options using importance sampling and stratification/ Quasi-Monte Carlo 失效
标题翻译：使用重要性抽样和分层/准蒙特卡罗的期权定价
公开(公告)号：US06381586B1
公开(公告)日：2002-04-30
申请号：US09209245
申请日：1998-12-10
申请人： Paul Glasserman , Philip Heidelberger , Nayyar P. Shahabuddin
发明人： Paul Glasserman , Philip Heidelberger , Nayyar P. Shahabuddin
IPC分类号： G06F1760
CPC分类号： G06F17/18 , G06Q40/00 , G06Q40/04 , G06Q40/06
摘要： A computer implemented method prices derivative securities (for example, options) by selecting an importance sampling (IS) distribution and combining the chosen IS distribution with stratified sampling. The process consists of the steps of choosing an importance sampling distribution and combining the chosen importance sampling with stratification or Quasi-Monte Carlo (QMC) simulation. In the first step, an importance sampling distribution is chosen. In the second step, the chosen importance sampling is combined with stratification or Quasi-Monte Carlo sequencing. The pricing of many types of securities reduces to one of estimating an expectation of a real-valued function of some random variables.
摘要翻译：计算机实施的方法通过选择重要性抽样（IS）分布并将选择的IS分布与分层采样相结合来定价衍生证券（例如，期权）。该过程包括以下步骤：选择重要性抽样分布，并将选择的重要性抽样与分层或准蒙特卡罗（QMC）模拟相结合。在第一步中，选择重要性抽样分布。在第二步中，选择的重要性抽样与分层或准蒙特卡罗测序相结合。许多类型的证券的定价减少到估计一些随机变量的实值函数的期望值之一。

75. 发明授权

US09037669B2 Remote processing and memory utilization 有权
标题翻译：远程处理和内存利用
公开(公告)号：US09037669B2
公开(公告)日：2015-05-19
申请号：US13570916
申请日：2012-08-09
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F15/167 , G06F15/173 , G06F11/00 , G06F9/54 , H04L29/06
CPC分类号： G06F9/547 , H04L29/0617 , H04L67/40
摘要： According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.
摘要翻译：根据本发明的一个实施例，一种用于操作存储器的系统包括由网络耦合到第二节点的第一节点，所述系统被配置为执行一种方法，该方法包括从所述第二节点接收来自所述第二节点的处理元件中的所述远程事务消息第一节点经由网络，其中当所述远程事务消息被传送到所述处理元件时，所述远程事务消息绕过所述第一节点中的主处理器。此外，该方法包括基于远程事务消息，由处理元件访问来自第一节点中的存储器中的位置的数据，以及由处理元件基于数据和远程事务消息执行计算。

76. 发明授权

US08977669B2 Multi-input and binary reproducible, high bandwidth floating point adder in a collective network 有权
标题翻译：集成网络中的多输入和二进制可重复的高带宽浮点加法器
公开(公告)号：US08977669B2
公开(公告)日：2015-03-10
申请号：US12684776
申请日：2010-01-08
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , Burkhard Steinmacher-Burow
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , Burkhard Steinmacher-Burow
IPC分类号： G06F7/38 , G06F9/30 , G06F9/38
CPC分类号： G06F7/38 , G06F7/485 , G06F9/30014 , G06F9/30025 , G06F9/3885 , G06F2207/3808
摘要： To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective logic devices converts the floating point numbers to integer numbers. The collective logic device adds the integer numbers and generating a summation of the integer numbers. The collective logic device converts the summation to a floating point number. The collective logic device performs the receiving, the converting the floating point numbers, the adding, the generating and the converting the summation in one pass. One pass indicates that the computing nodes send inputs only once to the collective logic device and receive outputs only once from the collective logic device.
摘要翻译：为了在并行计算系统中添加浮点数，集体逻辑器件从计算节点接收浮点数。集体逻辑器件将浮点数转换为整数。集体逻辑器件添加整数并产生整数的求和。集体逻辑设备将求和转换为浮点数。集体逻辑设备执行接收，转换浮点数，加法，生成和一次转换求和。一次通过表示计算节点仅向集体逻辑设备发送一次输入，并从集体逻辑设备接收一次输出。

77. 发明授权

US08892824B2 Store-operate-coherence-on-value 有权
标题翻译：存储操作一致性值
公开(公告)号：US08892824B2
公开(公告)日：2014-11-18
申请号：US12986652
申请日：2011-01-07
申请人： Dong Chen , Philip Heidelberger , Sameer Kumar , Martin Ohmacht , Burkhard Steinmacher-Burow
发明人： Dong Chen , Philip Heidelberger , Sameer Kumar , Martin Ohmacht , Burkhard Steinmacher-Burow
IPC分类号： G06F12/02 , G06F9/30 , G06F12/08 , G06F9/38
CPC分类号： G06F12/0815 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/3834 , Y02D10/13
摘要： A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.
摘要翻译：一种用于在包括多个处理器和至少一个高速缓冲存储器设备的并行计算环境中执行各种存储操作指令的系统，方法和计算机程序产品。系统中的队列从处理器接收存储操作指令，该指令指定在哪个条件下调用高速缓存一致性操作。系统中的硬件单元运行接收到的存储操作指令。硬件单元评估运行接收到的存储操作指令的结果是否满足条件。如果结果满足条件，则硬件单元调用与接收到的存储操作指令相关联的高速缓存存储器地址的高速缓存一致性操作。否则，硬件单元不会调用高速缓存存储器设备上的高速缓存一致性操作。

78. 发明授权

US08838944B2 Fast concurrent array-based stacks, queues and deques using fetch-and-increment-bounded, fetch-and-decrement-bounded and store-on-twin synchronization primitives 有权
标题翻译：快速并发的基于阵列的堆栈，使用获取和增量限制，获取和减少限制和存储双同步原语的队列和字符串
公开(公告)号：US08838944B2
公开(公告)日：2014-09-16
申请号：US12564535
申请日：2009-09-22
申请人： Dong Chen , Alana Gara , Philip Heidelberger , Sameer Kumar , Martin Ohmacht , Burkhard Steinmacher-Burow , Robert Wisniewski
发明人： Dong Chen , Alana Gara , Philip Heidelberger , Sameer Kumar , Martin Ohmacht , Burkhard Steinmacher-Burow , Robert Wisniewski
IPC分类号： G06F9/52 , G06F9/54
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/526 , G06F9/546
摘要： Implementation primitives for concurrent array-based stacks, queues, double-ended queues (deques) and wrapped deques are provided. In one aspect, each element of the stack, queue, deque or wrapped deque data structure has its own ticket lock, allowing multiple threads to concurrently use multiple elements of the data structure and thus achieving high performance. In another aspect, new synchronization primitives FetchAndIncrementBounded (Counter, Bound) and FetchAndDecrementBounded (Counter, Bound) are implemented. These primitives can be implemented in hardware and thus promise a very fast throughput for queues, stacks and double-ended queues.
摘要翻译：提供了基于并发数组的堆栈，队列，双端队列（deques）和包装deques的实现原语。在一个方面，堆栈，队列，deque或包装的deque数据结构的每个元素都有自己的票证锁定，允许多个线程同时使用数据结构的多个元素，从而实现高性能。在另一方面，实现新的同步原语FetchAndIncrementBounded（Counter，Bound）和FetchAndDecrementBounded（Counter，Bound）。这些原语可以在硬件中实现，从而为队列，堆栈和双端队列提供非常快的吞吐量。

79. 发明授权

US08655962B2 Shared address collectives using counter mechanisms 失效
标题翻译：共享地址集合使用计数器机制
公开(公告)号：US08655962B2
公开(公告)日：2014-02-18
申请号：US12568115
申请日：2009-09-28
申请人： Michael Blocksome , Gabor Dozsa , Thomas M. Gooding , Philip Heidelberger , Sameer Kumar , Amith R. Mamidala , Douglas Miller
发明人： Michael Blocksome , Gabor Dozsa , Thomas M. Gooding , Philip Heidelberger , Sameer Kumar , Amith R. Mamidala , Douglas Miller
IPC分类号： G06F15/16 , G06F15/167
CPC分类号： G06F9/544
摘要： A shared address space on a compute node stores data received from a network and data to transmit to the network. The shared address space includes an application buffer that can be directly operated upon by a plurality of processes, for instance, running on different cores on the compute node. A shared counter is used for one or more of signaling arrival of the data across the plurality of processes running on the compute node, signaling completion of an operation performed by one or more of the plurality of processes, obtaining reservation slots by one or more of the plurality of processes, or combinations thereof.
摘要翻译：计算节点上的共享地址空间存储从网络接收的数据和要发送到网络的数据。共享地址空间包括可以通过多个进程直接操作的应用缓冲器，例如在计算节点上的不同核上运行。共享计数器用于通过在计算节点上运行的多个进程的信令到达的一个或多个，信令完成由多个进程中的一个或多个执行的操作，通过一个或多个多个处理或其组合。

80. 发明授权

US08447960B2 Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition 失效
标题翻译：通过外部逻辑监视轮询循环退出时间条件，在引脚断言时暂停和激活线程状态
公开(公告)号：US08447960B2
公开(公告)日：2013-05-21
申请号：US12684860
申请日：2010-01-08
申请人： Dong Chen , Mark Giampapa , Philip Heidelberger , Martin Ohmacht , David L. Satterfield , Burkhard Steinmacher-Burow , Krishnan Sugavanam
发明人： Dong Chen , Mark Giampapa , Philip Heidelberger , Martin Ohmacht , David L. Satterfield , Burkhard Steinmacher-Burow , Krishnan Sugavanam
IPC分类号： G06F9/48
CPC分类号： G06F9/30079 , G06F9/3851
摘要： A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.
摘要翻译：一种用于增强计算机性能的系统和方法，其包括包括数据存储装置的计算机系统。计算机系统包括存储在数据存储装置中的程序，程序的步骤由处理器执行。处理器处理来自程序的指令。处理器中的等待状态等待接收指定的数据。处理器中的线程具有暂停状态，其中处理器等待指定的数据。处理器中的引脚从线程的暂停状态启动返回到活动状态。逻辑电路在处理器外部，并且逻辑电路被配置为检测指定的条件。当使用逻辑电路检测到指定的条件时，引脚启动返回到线程的活动状态。

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