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1. 发明授权

US09137098B2 T-Star interconnection network topology 有权
标题翻译： T星互连网络拓扑
公开(公告)号：US09137098B2
公开(公告)日：2015-09-15
申请号：US13584300
申请日：2012-08-13
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
IPC分类号： H04L12/715 , H04L12/24
CPC分类号： H04L41/0663 , H04L41/12 , H04L41/145 , H04L45/04
摘要： According to one embodiment of the present invention, a method of constructing network communication for a grid of node groups is provided, the grid including an M dimensional grid, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one, wherein each node includes a router. The method includes directly connecting each node in each node group to every other node in the node group via intra-group links and directly connecting each node in each node group of the M dimensional grid to a node in each neighboring node group in the M dimensional grid via inter-group links.
摘要翻译：根据本发明的一个实施例，提供了一种为节点组网格构建网络通信的方法，所述网格包括M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N 大于1，其中每个节点包括路由器。该方法包括通过组内链路将每个节点组中的每个节点直接连接到节点组中的每个其他节点，并将M维网格的每个节点组中的每个节点直接连接到M维中的每个相邻节点组中的节点网格通过组间链接。

2. 发明申请

US20140044015A1 T-STAR INTERCONNECTION NETWORK TOPOLOGY 审中-公开
标题翻译： T-STAR互联网络拓扑
公开(公告)号：US20140044015A1
公开(公告)日：2014-02-13
申请号：US13584300
申请日：2012-08-13
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Philip Heidelberger , Robert M. Senger , Yutaka Sugawara
IPC分类号： H04L12/28
CPC分类号： H04L41/0663 , H04L41/12 , H04L41/145 , H04L45/04
摘要： According to one embodiment of the present invention, a method of constructing network communication for a grid of node groups is provided, the grid including an M dimensional grid, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one, wherein each node includes a router. The method includes directly connecting each node in each node group to every other node in the node group via intra-group links and directly connecting each node in each node group of the M dimensional grid to a node in each neighboring node group in the M dimensional grid via inter-group links.
摘要翻译：根据本发明的一个实施例，提供了一种为节点组网格构建网络通信的方法，所述网格包括M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N 大于1，其中每个节点包括路由器。该方法包括通过组内链路将每个节点组中的每个节点直接连接到节点组中的每个其他节点，并将M维网格的每个节点组中的每个节点直接连接到M维中的每个相邻节点组中的节点网格通过组间链接。

3. 发明授权

US08626957B2 Collective network for computer structures 有权
标题翻译：计算机结构集体网络
公开(公告)号：US08626957B2
公开(公告)日：2014-01-07
申请号：US13101566
申请日：2011-05-05
申请人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd E. Takken , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd E. Takken , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas
IPC分类号： G06F15/16
CPC分类号： H04L1/08 , G06F9/46 , G06F11/08 , G06F11/1423 , H03M13/09 , H04L1/0061 , H04L1/1607 , H04L1/1867 , H04L2001/0093 , H04L2001/0097
摘要： A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.
摘要翻译：一种用于实现互连处理节点之间的高速，低延迟全局集体通信的系统和方法。全局集体网络最优地使得能够在具有多个互连处理节点的计算机结构中执行并行算法操作期间执行集体缩减操作。包括通过链路互连网络节点的路由器设备，以便于在虚拟网络的节点处执行低延迟全局处理操作。全局集体网络可以被配置为以异步或同步方式提供全局屏障和中断功能。当在大规模并行超级计算结构中实现时，全局集体网络根据处理算法的需要在物理上和逻辑上可分割。

4. 发明授权

US08595554B2 Reproducibility in a multiprocessor system 有权
标题翻译：多处理器系统中的重现性
公开(公告)号：US08595554B2
公开(公告)日：2013-11-26
申请号：US12774475
申请日：2010-05-05
申请人： Ralph A. Bellofatto , Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Thomas A. Liebsch , Martin Ohmacht , Don D. Reed , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Ralph A. Bellofatto , Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Thomas A. Liebsch , Martin Ohmacht , Don D. Reed , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F11/00
CPC分类号： G06F1/10 , G06F11/2242
摘要： Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.
摘要翻译：如果问题是可重现的，通常会大大帮助解决问题。为了确保多处理器系统的可重复性，提出了以下方面：确定性系统启动状态，单个系统时钟，系统中的时钟相位对齐，全系统同步事件，系统组件的可重复执行，确定性芯片接口，零 - 与系统进行通信，精确地停止系统并扫描系统状态。

5. 发明授权

US08407376B2 Recording a communication pattern and replaying messages in a parallel computing system 失效
标题翻译：记录通信模式并在并行计算系统中重播消息
公开(公告)号：US08407376B2
公开(公告)日：2013-03-26
申请号：US12500715
申请日：2009-07-10
申请人： Philip Heidelberger , Sameer Kumar
发明人： Philip Heidelberger , Sameer Kumar
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A parallel computer system includes a plurality of compute nodes. Each of the compute nodes includes at least one processor, at least one memory, and a direct memory address engine coupled to the at least one processor and the at least one memory. The system also includes a network interconnecting the plurality of compute nodes. The network operates a global message-passing application for performing communications across the network. Local instances of the global message-passing application operate at each of the compute nodes to carry out local processing operations independent of processing operations carried out at another one of the compute nodes. The direct memory address engines are configured to interact with the local instances of the global message-passing application via injection FIFO metadata describing an injection FIFO in a corresponding one of the memories. The local instances of the global message passing application are configured to record, in the injection FIFO in the corresponding one of the memories, message descriptors associated with messages of an arbitrary communication pattern in an iteration of an executing application program. The local instances of the global message passing application are configured to replay the message descriptors during a subsequent iteration of the executing application program.
摘要翻译：并行计算机系统包括多个计算节点。每个计算节点包括耦合到至少一个处理器和至少一个存储器的至少一个处理器，至少一个存储器和直接存储器地址引擎。该系统还包括互连多个计算节点的网络。该网络运行全球消息传递应用程序，用于跨网络执行通信。全局消息传递应用的本地实例在每个计算节点处操作，以独立于在另一个计算节点处执行的处理操作来执行本地处理操作。直接存储器地址引擎被配置为通过描述在对应的一个存储器中的注入FIFO的注入FIFO元数据与全局消息传递应用的本地实例进行交互。全局消息传递应用程序的本地实例被配置为在执行的应用程序的迭代中在对应的一个存储器中的注入FIFO中记录与任意通信模式的消息相关联的消息描述符。全局消息传递应用程序的本地实例被配置为在执行的应用程序的后续迭代期间重播消息描述符。

6. 发明授权

US08255638B2 Snoop filter for filtering snoop requests 失效
标题翻译：用于过滤窥探请求的Snoop过滤器
公开(公告)号：US08255638B2
公开(公告)日：2012-08-28
申请号：US12113262
申请日：2008-05-01
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk I. Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk I. Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos M. Vranas
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0822 , G06F12/0831 , G06F2212/507 , Y02D10/13
摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports, each port snoop filter implementing one or more parallel operating sub-filter elements that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.
摘要翻译：一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联并与之可操作地相连的一个或多个本地高速缓冲存储器。该方法包括提供与每个处理单元相关联的窥探过滤器设备，每个窥探过滤器设备具有多个专用输入端口，用于从多处理器计算环境中的专用存储器写入源接收窥探请求。每个窥探过滤器装置包括与多个专用输入端口相对应的多个并行操作端口窥探滤波器，每个端口窥探滤波器实现一个或多个并行操作子滤波器元件，其适于同时滤除从相应专用存储器接收的窥探请求写入源并将这些请求的子集转发到其相关联的处理单元。

7. 发明授权

US08122197B2 Managing coherence via put/get windows 失效
标题翻译：通过put / get窗口管理一致性
公开(公告)号：US08122197B2
公开(公告)日：2012-02-21
申请号：US12543890
申请日：2009-08-19
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
摘要翻译：一种用于管理多处理器计算机系统的两个处理器节点的两个处理器之间的相干性的方法和装置。通常，本发明涉及一种软件算法，其简化并显着加速了传送并行计算机的消息中的高速缓存一致性的管理以及辅助该高速缓存一致性算法的硬件设备。软件算法使用put / get窗口的打开和关闭来协调激活的所需要的，以实现缓存一致性。硬件设备可以是硬件地址解码的扩展，其在节点的物理存储器地址空间中创建（a）实际不存在的虚拟存储器的区域，并且（b）因此能够立即响应从处理元素读取和写入请求。

8. 发明授权

US08112559B2 Increasing available FIFO space to prevent messaging queue deadlocks in a DMA environment 有权
标题翻译：增加可用的FIFO空间，以防止DMA环境中的消息队列死锁
公开(公告)号：US08112559B2
公开(公告)日：2012-02-07
申请号：US12241634
申请日：2008-09-30
申请人： Michael A. Blocksome , Dong Chen , Thomas Gooding , Philip Heidelberger , Jeff Parker
发明人： Michael A. Blocksome , Dong Chen , Thomas Gooding , Philip Heidelberger , Jeff Parker
IPC分类号： G06F13/28 , G06F15/167
CPC分类号： G06F13/28
摘要： Embodiments of the invention may be used to manage message queues in a parallel computing environment to prevent message queue deadlock. A direct memory access controller of a compute node may determine when a messaging queue is full. In response, the DMA may generate an interrupt. An interrupt handler may stop the DMA and swap all descriptors from the full messaging queue into a larger queue (or enlarge the original queue). The interrupt handler then restarts the DMA. Alternatively, the interrupt handler stops the DMA, allocates a memory block to hold queue data, and then moves descriptors from the full messaging queue into the allocated memory block. The interrupt handler then restarts the DMA. During a normal messaging advance cycle, a messaging manager attempts to inject the descriptors in the memory block into other messaging queues until the descriptors have all been processed.
摘要翻译：本发明的实施例可以用于在并行计算环境中管理消息队列以防止消息队列死锁。计算节点的直接存储器访问控制器可以确定消息队列何时已满。作为响应，DMA可能会产生中断。中断处理程序可能会停止DMA，并将所有描述符从完整消息队列交换到更大的队列（或放大原始队列）。然后中断处理程序重新启动DMA。或者，中断处理程序停止DMA，分配存储块来保存队列数据，然后将描述符从完整消息队列移动到分配的内存块中。然后中断处理程序重新启动DMA。在正常消息传递提前周期期间，消息收发管理器尝试将描述符注入到其他消息队列中，直到描述符全部被处理。

9. 发明授权

US08001280B2 Collective network for computer structures 有权
标题翻译：计算机结构集体网络
公开(公告)号：US08001280B2
公开(公告)日：2011-08-16
申请号：US11572372
申请日：2005-07-18
申请人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd E. Takken , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Paul W. Coteus , Dong Chen , Alan Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Todd E. Takken , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas
IPC分类号： G06F15/16
CPC分类号： G06F15/17381 , H04L1/1845 , H04L12/4641
摘要： A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices ate included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.
摘要翻译：一种用于实现互连处理节点之间的高速，低延迟全局集体通信的系统和方法。全局集体网络最优地使得能够在具有多个互连处理节点的计算机结构中执行并行算法操作期间执行集体缩减操作。路由器设备包括通过链路互连网络的节点，以便于在虚拟网络和类结构的节点处执行低延迟全局处理操作。全局集体网络可以被配置为以异步或同步方式提供全局屏障和中断功能。当在大规模并行超级计算结构中实现时，全局集体网络根据处理算法的需要在物理上和逻辑上可分割。

10. 发明申请

US20110173399A1 DISTRIBUTED PARALLEL MESSAGING FOR MULTIPROCESSOR SYSTEMS 失效
标题翻译：用于多处理器系统的分布式并行消息传递
公开(公告)号：US20110173399A1
公开(公告)日：2011-07-14
申请号：US12693972
申请日：2010-01-26
申请人： Dong Chen , Philip Heidelberger , Valentina Salapura , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Philip Heidelberger , Valentina Salapura , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F15/16 , G06F12/02 , G06F15/173 , G06F15/76 , G06F9/06
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： A method and apparatus for distributed parallel messaging in a parallel computing system. The apparatus includes, at each node of a multiprocessor network, multiple injection messaging engine units and reception messaging engine units, each implementing a DMA engine and each supporting both multiple packet injection into and multiple reception from a network, in parallel. The reception side of the messaging unit (MU) includes a switch interface enabling writing of data of a packet received from the network to the memory system. The transmission side of the messaging unit, includes switch interface for reading from the memory system when injecting packets into the network.
摘要翻译：一种并行计算系统中分布式并行消息传递的方法和装置。该装置在多处理器网络的每个节点处包括多个注入消息传递引擎单元和接收消息传递引擎单元，每个实现一个DMA引擎，并且每个支持同时支持来自网络的多个分组注入和多个接收。消息接收单元（MU）的接收侧包括能够将从网络接收到的分组的数据写入存储器系统的切换接口。消息传送单元的发送侧包括用于在将分组注入网络时从存储器系统读取的切换接口。

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