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1. 发明授权

US5708793A Method and apparatus using address and read head location information to provide optimal operation of a disk system 失效
公开(公告)号：US5708793A
公开(公告)日：1998-01-13
申请号：US414409
申请日：1995-03-31
申请人： Peter Anthony Franaszek , John Timothy Robinson
发明人： Peter Anthony Franaszek , John Timothy Robinson
IPC分类号： G06F3/06 , G06F12/00
CPC分类号： G06F3/0611 , G06F3/064 , G06F3/0674
摘要： Minimal random disk write latency is achieved by limiting the number of logical address blocks that can be serviced by a disk to less that the actual number of physically addressable blocks of the system and having a disk controller dynamically map logical data blocks to physical disk blocks in such a fashion that each logical write can take place to any free location, where the free location can be chosen in any track of the current cylinder.

2. 发明授权

US08122216B2 Systems and methods for masking latency of memory reorganization work in a compressed memory system 失效
标题翻译：用于屏蔽存储器重组延迟的系统和方法在压缩存储器系统中工作
公开(公告)号：US08122216B2
公开(公告)日：2012-02-21
申请号：US11516207
申请日：2006-09-06
申请人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
发明人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/08 , G06F12/0804 , G06F12/1408 , G06F2212/401
摘要： Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.
摘要翻译：提供了计算机存储器管理系统和方法，其中在压缩存储器系统中利用数据块缓冲和优先级调度协议来掩盖在访问压缩主存储器之后与存储器重组工作相关联的等待时间。特别地，实现数据块缓冲器和优先级调度协议以延迟和优先化存储器重组工作，以允许资源用于服务新的存储器访问请求和其他高优先级命令。

3. 发明授权

US06804754B1 Space management in compressed main memory 失效
标题翻译：压缩主存储器中的空间管理
公开(公告)号：US06804754B1
公开(公告)日：2004-10-12
申请号：US08859865
申请日：1997-05-21
申请人： Peter Anthony Franaszek , Michel Henri Theodore Hack , Charles Otto Schulz , Thomas Basil Smith, III
发明人： Peter Anthony Franaszek , Michel Henri Theodore Hack , Charles Otto Schulz , Thomas Basil Smith, III
IPC分类号： G06F1200
CPC分类号： G06F12/08 , G06F12/023 , G06F2212/401
摘要： Memory is managed by controlling the expansion of memory contents, especially in those computing environments in which the memory contents are compressed. Control is provided by imposing some restrictions to memory references outside a specified subset of the memory contents, and by controlling the transfer of items into the subset. In one example, the transfer of items into the subset is based on a function of parameters, including an estimate of the amount of free space in the memory.
摘要翻译：通过控制存储器内容的扩展来管理存储器，特别是在存储器内容被压缩的那些计算环境中。通过对存储器内容的指定子集之外的存储器引用施加一些限制，并且通过控制将项目传送到子集来提供控制。在一个示例中，将项目转移到子集中是基于参数的函数，包括对存储器中的可用空间量的估计。

4. 发明授权

US06215412B1 All-node switch-an unclocked, unbuffered, asynchronous switching apparatus 失效
标题翻译：全节点交换机 - 一个非锁定的，无缓冲的异步交换设备
公开(公告)号：US06215412B1
公开(公告)日：2001-04-10
申请号：US08457789
申请日：1995-06-02
申请人： Peter Anthony Franaszek , Christos John Georgiou , Robert Francis Lusch , Joseph Michael Mosley , Howard Thomas Olnowich
发明人： Peter Anthony Franaszek , Christos John Georgiou , Robert Francis Lusch , Joseph Michael Mosley , Howard Thomas Olnowich
IPC分类号： H04Q100
CPC分类号： H04L1/0057 , G06F11/261 , G06F13/4022 , G06F15/17375 , G06F15/17393 , H04L7/0338 , H04L49/101 , H04L49/15 , H04L49/1523 , H04L49/201 , H04L49/25 , H04L49/254 , H04L49/40 , H04L49/555 , H04Q11/0066 , H04Q11/0478
摘要： A new asynchronous approach used to quickly and dynamically switch input port connections to output port connections and to resolve contention. The switch is self-routing in two cycle times at the same high speed serial rate that data is transferred through the switch. The normal mode of the switch requires absolutely no synchronization amongst any of the input and output ports which interface to the switch. The switch is void of centrally controlled clocking and any data buffering. Data traverses the switch only encountering three gate delays—on-chip receiver, mux, and off-chip driver. Contention is detected and resolved on chip, and yet the logic implementation is extremely simple and low in gate count, so the switch design is never gate limited. The protocol requires several parallel data lines plus two or three control lines.
摘要翻译：一种新的异步方法，用于快速，动态地将输入端口连接切换到输出端口连接并解决争用。交换机以两个周期的时间自动路由，数据通过交换机传输相同的高速串行速率。交换机的正常模式在与交换机接口的任何输入和输出端口之间绝对不同步。该开关没有集中控制的时钟和任何数据缓冲。数据穿越开关只遇到三个门延迟片上接收器，多路复用器和片外驱动器。在芯片上检测和解决争用，但逻辑实现非常简单，门数较少，因此开关设计从不限制门限。该协议需要多条并行数据线加上两条或三条控制线。

5. 发明授权

US5654695A Multi-function network 失效
标题翻译：多功能网络
公开(公告)号：US5654695A
公开(公告)日：1997-08-05
申请号：US606232
申请日：1996-02-23
申请人： Howard Thomas Olnowich , Thomas Norman Barker , Peter Anthony Franaszek , Philip Heidelberger , Bharat Deep Rathi , Anujan Mangala Varma
发明人： Howard Thomas Olnowich , Thomas Norman Barker , Peter Anthony Franaszek , Philip Heidelberger , Bharat Deep Rathi , Anujan Mangala Varma
IPC分类号： G06F11/26 , G06F13/40 , G06F15/173 , G06F17/50 , H03M9/00 , H04L1/00 , H04L7/033 , H04L7/04 , H04L12/18 , H04L12/56 , H04Q11/00 , H04Q11/04 , H04Q1/00
CPC分类号： H04L7/0338 , G06F13/4022 , G06F15/17375 , G06F15/17393 , G06F17/5022 , H03M9/00 , H04L1/0057 , H04L49/1515 , H04L7/044 , H04Q11/0478 , G06F11/261 , H04L49/101 , H04L49/205 , H04L49/254 , H04Q11/0066
摘要： A multi-stage architecture for providing a single switching component in multiplicity to create a single network capable of performing a multiplicity of functions. One function of the disclosed network is to circumvent the traditional blocking problems in multi-stage networks by implementing ALTERNATE PATHS between devices within the same network. This permits a non-blocked path between 2 devices to be found by rearrangeability--the act of trying or searching different alternate paths until a non-blocked connection is established. A second network function permits a special high priority mode of transfer which will guarantee that the connection will be made to an idle device as rapidly as possible.
摘要翻译：一种多级架构，用于提供多重性的单个交换组件以创建能够执行多种功能的单个网络。所公开网络的一个功能是通过在同一网络内的设备之间实现ALTERNATE PATHS来规避多级网络中传统的阻塞问题。这允许通过可重新排列来找到2个设备之间的非阻塞路径 - 尝试或搜索不同的备用路径直到建立非阻塞连接的行为。第二网络功能允许特殊的高优先级传输模式，这将保证尽可能快地连接到空闲设备。

6. 发明授权

US4052704A Apparatus for reordering the sequence of data stored in a serial memory 失效
标题翻译：用于重新记录存储在串行存储器中的数据的装置
公开(公告)号：US4052704A
公开(公告)日：1977-10-04
申请号：US752752
申请日：1976-12-20
申请人： Peter Anthony Franaszek
发明人： Peter Anthony Franaszek
IPC分类号： G11C19/00 , G06F7/78 , G06F12/00 , G06F7/04
CPC分类号： G06F7/78
摘要： This memory management system provides an improved search logic for locating pages of data stored parallel-by-bit, serially-by-page in a shift register memory and for moving those pages to a position at the head of the file. Searching alternates between forward and reverse with a first direction change occurring when the head of the file occupies an input/output station in the memory and a second change occurring when the last of a plurality of pages identified for search at the first reversal position is found.The page numbers of three sought data pages are entered into three search registers and compared with the page number of each page as it is shifted into the input/output station of the memory. A page number is replaced when the page is found. Page numbers are marked with a binary one upon each direction change at the first position and with a binary zero at each replacement of a page number at other than that position.The data loop includes four parking registers which may be selectively excluded from the loop so as to park the successive pages as they are found in the search. As a reverse feeding moves the head of the file proximate to the input/output station, the pages stored in the parking registers are inserted into the data stream at the head of the file.

7. 发明申请

US20080059728A1 Systems and methods for masking latency of memory reorganization work in a compressed memory system 失效
标题翻译：用于屏蔽存储器重组延迟的系统和方法在压缩存储器系统中工作
公开(公告)号：US20080059728A1
公开(公告)日：2008-03-06
申请号：US11516207
申请日：2006-09-06
申请人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
发明人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
IPC分类号： G06F13/28
CPC分类号： G06F12/08 , G06F12/0804 , G06F12/1408 , G06F2212/401
摘要： Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.
摘要翻译：提供了计算机存储器管理系统和方法，其中在压缩存储器系统中利用数据块缓冲和优先级调度协议来掩盖在访问压缩主存储器之后与存储器重组工作相关联的等待时间。特别地，实现数据块缓冲器和优先级调度协议以延迟和优先化存储器重组工作，以允许资源用于服务新的存储器访问请求和其他高优先级命令。

8. 发明授权

US5761536A System and method for reducing memory fragmentation by assigning remainders to share memory blocks on a best fit basis 失效
标题翻译：通过分配余数以最佳匹配的方式共享内存块来减少内存碎片的系统和方法
公开(公告)号：US5761536A
公开(公告)日：1998-06-02
申请号：US701143
申请日：1996-08-21
申请人： Peter Anthony Franaszek
发明人： Peter Anthony Franaszek
IPC分类号： G06F12/02 , G06F7/00
CPC分类号： G06F12/023 , G06F2212/401
摘要： A system and method for storing variable length objects such that memory fragmentation is reduced, while avoiding the need for memory reorganization. A remainder of a variable length object may be assigned to share a fixed-size block of storage with a remainder from another variable length object (two such remainders which share a block are referred to as roommates) on a best fit or first fit basis. One remainder is stored at one end of the block, while the other remainder is stored at the other end of the block. The variable length objects which are to share a block of storage are selected from the same cohort. Thus, there is some association between the objects. This association may be that the objects are from the same page or are in some linear order spanning multiple pages, as examples. Information regarding the variable length objects of a cohort, such as whether an object has a roommate, is stored in memory.
摘要翻译：用于存储可变长度对象的系统和方法，使得减少内存碎片，同时避免对存储器重组的需要。可以分配可变长度对象的剩余部分以最佳拟合或第一拟合的基础来共享来自另一个可变长度对象（其中共享一个块的两个这样的剩余部分被称为室友）的固定大小的存储块。一个余数存储在块的一端，而另一个余数存储在块的另一端。从同一个群组中选择共享一个存储块的可变长度对象。因此，对象之间存在一些关联。该关联可能是对象来自相同的页面，或者是跨越多个页面的一些线性顺序，例如。关于队列的可变长度对象（例如对象是否具有室友）的信息被存储在存储器中。

9. 发明授权

US4028535A Apparatus and method for generating a data code with a spectral null 失效
标题翻译：用于产生具有频谱零点的数据码的装置和方法
公开(公告)号：US4028535A
公开(公告)日：1977-06-07
申请号：US695295
申请日：1976-06-11
申请人： Peter Anthony Franaszek , David Allen Thompson
发明人： Peter Anthony Franaszek , David Allen Thompson
IPC分类号： H03M5/14 , G11B20/14 , H03M7/00 , H03M7/04 , H03M7/14 , H04L25/49 , G06F13/04 , G06F7/38 , G06F15/34
CPC分类号： G11B20/1426 , H04L25/4906
摘要： In a dynamic disc memory system, servo signal tracks and data tracks are adjacent. The servo track includes a signal having a predetermined frequency. With the system and method of this disclosure, the data recorded on the data track is translated to have a frequency null at the frequency of the servo signal track by translating apparatus to eliminate cross-talk at the servo frequency.
摘要翻译：在动态盘存储器系统中，伺服信号轨道和数据轨迹相邻。伺服磁道包括具有预定频率的信号。利用本公开的系统和方法，记录在数据磁道上的数据被转换为在伺服信号轨道的频率处通过转换装置使频率为零，以消除伺服频率的串扰。

10. 发明授权

US07962700B2 Systems and methods for reducing latency for accessing compressed memory using stratified compressed memory architectures and organization 有权
标题翻译：使用分层压缩内存架构和组织来减少访问压缩内存的延迟的系统和方法
公开(公告)号：US07962700B2
公开(公告)日：2011-06-14
申请号：US11516188
申请日：2006-09-06
申请人： Peter Anthony Franaszek , Luis Alfonso Lastras-Montano , Robert Brett Tremaine
发明人： Peter Anthony Franaszek , Luis Alfonso Lastras-Montano , Robert Brett Tremaine
IPC分类号： G06F13/12 , G06F12/00 , G06F9/26 , G06F11/00 , G09G5/00
CPC分类号： G06T1/60 , G06F12/0897 , G06F12/1081 , G06F2212/401 , G11C7/1006 , G11C2207/102
摘要： Compressed memory systems are provided to reduce latency associated with accessing compressed memory using stratified compressed memory architectures and memory organization protocols in which a region of compressed main memory is allocated as a direct access memory (DAM) region for storing uncompressed data items. The uncompressed data items in the DAM region can be directly accessed, speculatively, to serve access requests to main memory, requiring access to compressed memory in the event of a DAM miss.
摘要翻译：提供压缩存储器系统以减少使用分层压缩存储器架构和存储器组织协议访问压缩存储器的延迟，其中压缩主存储器的区域被分配为用于存储未压缩数据项的直接存取存储器（DAM）区域。可以直观地访问DAM区域中的未压缩数据项，从而提供对主存储器的访问请求，在遇到DAM缺失时需要访问压缩存储器。

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