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1. 发明申请

US20140047060A1 REMOTE PROCESSING AND MEMORY UTILIZATION 有权
标题翻译：远程处理和存储器的使用
公开(公告)号：US20140047060A1
公开(公告)日：2014-02-13
申请号：US13570916
申请日：2012-08-09
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F15/167
CPC分类号： G06F9/547 , H04L29/0617 , H04L67/40
摘要： According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.
摘要翻译：根据本发明的一个实施例，一种用于操作存储器的系统包括由网络耦合到第二节点的第一节点，所述系统被配置为执行一种方法，该方法包括从所述第二节点接收来自所述第二节点的处理元件中的所述远程事务消息第一节点经由网络，其中当所述远程事务消息被传送到所述处理元件时，所述远程事务消息绕过所述第一节点中的主处理器。此外，该方法包括基于远程事务消息，由处理元件访问来自第一节点中的存储器中的位置的数据，以及由处理元件基于数据和远程事务消息执行计算。

2. 发明授权

US09037669B2 Remote processing and memory utilization 有权
标题翻译：远程处理和内存利用
公开(公告)号：US09037669B2
公开(公告)日：2015-05-19
申请号：US13570916
申请日：2012-08-09
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F15/167 , G06F15/173 , G06F11/00 , G06F9/54 , H04L29/06
CPC分类号： G06F9/547 , H04L29/0617 , H04L67/40
摘要： According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.
摘要翻译：根据本发明的一个实施例，一种用于操作存储器的系统包括由网络耦合到第二节点的第一节点，所述系统被配置为执行一种方法，该方法包括从所述第二节点接收来自所述第二节点的处理元件中的所述远程事务消息第一节点经由网络，其中当所述远程事务消息被传送到所述处理元件时，所述远程事务消息绕过所述第一节点中的主处理器。此外，该方法包括基于远程事务消息，由处理元件访问来自第一节点中的存储器中的位置的数据，以及由处理元件基于数据和远程事务消息执行计算。

3. 发明授权

US08725993B2 Thread transition management 失效
标题翻译：线程转换管理
公开(公告)号：US08725993B2
公开(公告)日：2014-05-13
申请号：US13032737
申请日：2011-02-23
申请人： Christopher M. Abernathy , Mary D. Brown , Susan E. Eisen , James A. Kahle , Hung Q. Le , Dung Q. Nguyen
发明人： Christopher M. Abernathy , Mary D. Brown , Susan E. Eisen , James A. Kahle , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3013 , G06F9/384 , G06F9/3851 , G06F9/461
摘要： Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.
摘要翻译：可以使用各种系统，过程，产品和技术来管理线程转换。在特定实现中，用于管理线程转换的系统和过程可以包括确定要对两个数据寄存器组的相对使用进行转换的能力，并且基于转换确定来确定是否将线程数据移入至少一个数据寄存器设置为二级寄存器。系统和过程还可以包括基于移动确定将线程数据从至少一个数据寄存器集合移动到第二级寄存器的能力。

4. 发明申请

US20120096084A1 SHARED MEDIA EXPERIENCE DISTRIBUTION AND PLAYBACK 有权
标题翻译：共享媒体经验分发与回放
公开(公告)号：US20120096084A1
公开(公告)日：2012-04-19
申请号：US12903840
申请日：2010-10-13
申请人： Travis M. Grigsby , James A. Kahle , Michael A. Paolini
发明人： Travis M. Grigsby , James A. Kahle , Michael A. Paolini
IPC分类号： G06F15/16
CPC分类号： H04N21/42203 , G06Q50/01 , H04N21/4307 , H04N21/441 , H04N21/4532 , H04N21/4622 , H04N21/4788 , H04N21/8106
摘要： Embodiments of the present invention provide a method, system and computer program product for providing a shared user experience during media playback. In an embodiment of the invention, a method for providing a shared user experience during media playback is provided. The method includes selecting for a particular user a media file for playback in a media player executing in memory by a processor of a computer. The method also includes retrieving a shared user experience audio file recorded for a different user during a previous playback of the selected media file. Finally, the method includes playing back for the particular user both the selected media file and the retrieved shared user experience audio file concurrently in the media player.
摘要翻译：本发明的实施例提供了一种用于在媒体播放期间提供共享用户体验的方法，系统和计算机程序产品。在本发明的实施例中，提供了一种用于在媒体回放期间提供共享用户体验的方法。该方法包括为特定用户选择一种媒体文件，用于在由计算机的处理器在存储器中执行的媒体播放器中回放。该方法还包括在所选择的媒体文件的先前播放期间检索为不同用户记录的共享用户体验音频文件。最后，该方法包括在媒体播放器中同时播放所选择的媒体文件和检索到的共享用户体验音频文件的特定用户。

5. 发明授权

US5867684A Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction 失效
标题翻译：允许并发执行存储多指令和依赖指令的方法和处理器
公开(公告)号：US5867684A
公开(公告)日：1999-02-02
申请号：US873013
申请日：1997-06-11
申请人： James A. Kahle , Albert J. Loper , Soummya Mallick , Aubrey D. Ogden
发明人： James A. Kahle , Albert J. Loper , Soummya Mallick , Aubrey D. Ogden
IPC分类号： G06F9/312 , G06F9/38 , G06F12/00
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F9/3838
摘要： A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, according to the present invention, a method of executing a store multiple instruction in a superscaler microprocessor is provided. This method comprises the steps of dispatching a store multiple instruction to a load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load store instruction stores data from a plurality of registers to memory; and executing a fixed point instruction that is dependent upon data being stored by the store multiple instruction from a register of the plurality of registers indicated by the fixed point instruction as a source register, prior to the store multiple instruction completing its execution, but prohibiting the executing fixed point instruction from writing to a register of the plurality of registers prior to the store multiple instruction completing.
摘要翻译：提供了一种在超标量微处理器中执行加载多指令的方法和装置。该方法包括以下步骤：向加载/存储单元发送加载多个指令，其中加载/存储单元开始执行分派的加载多个指令，并且其中加载多个指令将数据从存储器加载到多个寄存器中。该方法还包括维护列出多个寄存器的每个寄存器并且通过执行加载多个指令指示何时将数据加载到每个寄存器中的表的步骤。该方法通过在载入多个指令完成其执行之前执行依赖于由加载多个指令加载的源操作数数据到由指令指示的多个寄存器的寄存器中作为源寄存器的指令，当该表表示源操作数数据已加载到源寄存器中。此外，根据本发明，提供了一种在超标量微处理器中执行存储多重指令的方法。该方法包括以下步骤：将存储多重指令分派到加载/存储单元，从而加载/存储单元开始执行存储多指令，其中加载存储指令将数据从多个寄存器存储到存储器; 并且在存储多个指令完成其执行之前，执行依赖于由所述固定点指令指示的多个寄存器的寄存器作为源寄存器的存储多个指令存储的数据的固定点指令，但是禁止在存储多个指令完成之前，从写入到多个寄存器的寄存器执行固定点指令。

6. 发明授权

US5694565A Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions 失效
公开(公告)号：US5694565A
公开(公告)日：1997-12-02
申请号：US526343
申请日：1995-09-11
申请人： James A. Kahle , Albert J. Loper , Soummya Mallick , Aubrey D. Ogden
发明人： James A. Kahle , Albert J. Loper , Soummya Mallick , Aubrey D. Ogden
IPC分类号： G06F9/312 , G06F9/38 , G06F12/00
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F9/3838
摘要： A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, according to the present invention, a method of executing a store multiple instruction in a superscaler microprocessor is provided. This method comprises the steps of dispatching a store multiple instruction to a load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load store instruction stores data from a plurality of registers to memory; and executing a fixed point instruction that is dependent upon data being stored by the store multiple instruction from a register of the plurality of registers indicated by the fixed point instruction as a source register, prior to the store multiple instruction completing its execution, but prohibiting the executing fixed point instruction from writing to a register of the plurality of registers prior to the store multiple instruction completing.

7. 发明授权

US08516272B2 Secure dynamically reconfigurable logic 有权
标题翻译：安全动态可重构逻辑
公开(公告)号：US08516272B2
公开(公告)日：2013-08-20
申请号：US12827726
申请日：2010-06-30
申请人： H Peter Hofstee , James A. Kahle , Michael A. Paolini
发明人： H Peter Hofstee , James A. Kahle , Michael A. Paolini
IPC分类号： G06F11/30 , G06F15/16 , G06F15/177 , H04L12/28 , H04J3/02 , H04J3/16 , H04K1/00
CPC分类号： G06F21/76 , G06F15/7867
摘要： A mechanism for securely and dynamically reconfiguring reconfigurable logic is provided. A state machine within a data processing system establishes a hardware boundary to the reconfigurable logic within the data processing system thereby forming isolated reconfigurable logic. The state machine clears any prior state existing within the isolated reconfigurable logic. The state machine authenticates a new configuration to be loaded into the isolated reconfigurable logic. The state machine determines whether the authentication of the new configuration is successful. Responsive to the authentication of the new configuration being successful, the state machine loads the new configuration into the isolated reconfigurable logic. The state machine then starts operation of the isolated reconfigurable logic.
摘要翻译：提供了一种用于安全和动态地重新配置可重构逻辑的机制。数据处理系统内的状态机为数据处理系统内的可重构逻辑建立硬件边界，从而形成隔离的可重配置逻辑。状态机清除分离的可重新配置逻辑中存在的任何先前状态。状态机验证要加载到隔离可重配置逻辑中的新配置。状态机确定新配置的认证是否成功。响应于新配置的认证成功，状态机将新配置加载到隔离的可重配置逻辑中。状态机然后启动隔离的可重新配置逻辑的操作。

8. 发明授权

US06212542B1 Method and system for executing a program within a multiscalar processor by processing linked thread descriptors 失效
标题翻译：通过处理链接线程描述符来执行多级数据处理器内程序的方法和系统
公开(公告)号：US06212542B1
公开(公告)日：2001-04-03
申请号：US08767487
申请日：1996-12-16
申请人： James A. Kahle , Soummya Mallick , Robert G. McDonald , Edward L. Swarthout
发明人： James A. Kahle , Soummya Mallick , Robert G. McDonald , Edward L. Swarthout
IPC分类号： G06F900
CPC分类号： G06F9/4843 , G06F9/30087 , G06F9/3009 , G06F9/3851
摘要： A multiscalar processor and method of executing a multiscalar program within a multiscalar processor having a plurality of processing elements and a thread scheduler are provided. The multiscalar program includes a plurality of threads that are each composed of one or more instructions of a selected instruction set architecture. Each of the plurality of threads has a single entry point and a plurality of possible exit points. The multiscalar program further comprises thread code including a plurality of data structures that are each associated with a respective one of the plurality of threads. According to the method, a third data structure among the plurality of data structures is supplied to the thread scheduler. The third data structure, which is associated with a third thread among the plurality of threads, specifies a first data structure associated with a first possible exit point of the third thread and a second data structure associated with a second possible exit point of the third thread. The third thread is assigned to a selected one of the plurality of processing elements for execution. Prior to completing execution of the third thread, the thread scheduler selects from among the first and the second possible exit points of the third thread. In response to the selection, a corresponding one of the first and second data structures is loaded into the thread scheduler for processing.
摘要翻译：提供了一种在具有多个处理元件和线程调度器的多级数值处理器内执行多级计算机的多级数据处理器和方法。多节目程序包括多个线程，每个线程由所选择的指令集架构的一个或多个指令组成。多个线程中的每一个具有单个入口点和多个可能的出口点。多节目程序还包括线程代码，其包括多个数据结构，每个数据结构与多个线程中的相应一个线程相关联。根据该方法，将多个数据结构中的第三数据结构提供给线程调度器。与多个线程中的第三线程相关联的第三数据结构指定与第三线程的第一可能退出点相关联的第一数据结构和与第三线程的第二可能出口点相关联的第二数据结构。第三线程被分配给用于执行的多个处理元件中的所选择的一个。在完成第三线程的执行之前，线程调度器从第三线程的第一和第二可能出口点中选择。响应于该选择，第一和第二数据结构中相应的一个被加载到线程调度器中进行处理。

9. 发明授权

US5913925A Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order 失效
标题翻译：用于构建包括无序线程和处理器的程序的方法和系统以及执行无序线程的方法
公开(公告)号：US5913925A
公开(公告)日：1999-06-22
申请号：US767490
申请日：1996-12-16
申请人： James A. Kahle , Soummya Mallick , Robert G. McDonald
发明人： James A. Kahle , Soummya Mallick , Robert G. McDonald
IPC分类号： G06F9/44 , G06F9/48 , G06F9/38
CPC分类号： G06F9/4843 , G06F9/44
摘要： A method and system for constructing a program are provided. According to the method, each of a plurality of instructions are assigned to at least one of a plurality of threads. The plurality of threads include first, second, and third threads, where the third thread follows the first thread and precedes the second thread in a logical program order. A data structure associated with the first thread is then constructed. The data structure includes an indication that execution of the second thread is to be initiated prior to initiation of execution of the third thread. According to one embodiment, the indication within the data structure is a pointer that specifies a second data structure associated with the second thread.
摘要翻译：提供了一种用于构建程序的方法和系统。根据该方法，将多个指令中的每一个分配给多个线程中的至少一个。多个线程包括第一，第二和第三线程，其中第三线程遵循第一线程并且以逻辑程序顺序在第二线程之前。然后构建与第一线程相关联的数据结构。数据结构包括在开始执行第三线程之前要启动第二线程的执行的指示。根据一个实施例，数据结构内的指示是指定与第二线程相关联的第二数据结构的指针。

10. 发明授权

US10152450B2 Remote processing and memory utilization 有权
公开(公告)号：US10152450B2
公开(公告)日：2018-12-11
申请号：US13584323
申请日：2012-08-13
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F15/167 , G06F15/173 , G06F9/54 , H04L29/06 , H04L29/08
摘要： According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.

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