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1. 发明授权

US09037892B2 System-wide power management control via clock distribution network 有权
标题翻译：通过时钟分配网络进行全系统的电源管理控制
公开(公告)号：US09037892B2
公开(公告)日：2015-05-19
申请号：US13085879
申请日：2011-04-13
申请人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
发明人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
IPC分类号： G06F1/04 , G06F1/12 , G06F1/32 , G06F1/10 , G06F1/20
CPC分类号： G06F1/329 , G06F1/10 , G06F1/12 , G06F1/206 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D10/24
摘要： An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.
摘要翻译：一种用于自动控制包括多个处理器的并行计算系统的功耗的装置，方法和计算机程序产品。计算设备向并行计算系统发出命令。时钟脉冲宽度调制器对系统时钟信号中的命令进行编码，以分配给多个处理器。并行计算系统中的多个处理器接收包括编码命令的系统时钟信号，并根据编码命令调整功耗。

2. 发明授权

US08930752B2 Scheduler for multiprocessor system switch with selective pairing 有权
标题翻译：具有选择性配对的多处理器系统切换调度程序
公开(公告)号：US08930752B2
公开(公告)日：2015-01-06
申请号：US13027960
申请日：2011-02-15
申请人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
发明人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
IPC分类号： G06F11/00 , G06F11/16
CPC分类号： G06F11/1641 , G06F11/165 , G06F2201/845
摘要： System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.
摘要翻译：用于在具有选择性配对处理器核心的多处理系统中调度线程的系统，方法和计算机程序产品，用于提高处理可靠性。提供选择性配对设施，其选择性地连接，即配对多个微处理器或处理器核，以提供一个高度可靠的线程（或线程组）。该方法配置选择性配对设施以使用检查提供一个高度可靠的线程以实现高可靠性，并将线程分配给相应的处理器核心，指示需要进行硬件检查。该方法配置选择性配对工具以提供多个独立核心，并将线程分配给相应的处理器核心，指示固有的弹性。

3. 发明授权

US08671311B2 Multiprocessor switch with selective pairing 失效
标题翻译：具有选择性配对的多处理器开关
公开(公告)号：US08671311B2
公开(公告)日：2014-03-11
申请号：US13027882
申请日：2011-02-15
申请人： Alan Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F11/00
CPC分类号： G06F11/1641 , G06F11/1654 , G06F2201/845
摘要： System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory “nest” (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus.
摘要翻译：用于多处理系统的系统，方法和计算机程序产品，以提供处理器核心的选择性配对，以提高处理可靠性。提供选择性配对设施，其选择性地连接，即配对多个微处理器或处理器核，以提供一个高度可靠的线程（或线程组）。每个成对的微处理器或处理器核心提供一个高度可靠的线程，用于高可靠性与诸如存储器“嵌套”（或存储器层级），可选系统控制器和可选中断控制器的系统组件连接，可选的I / O或外设设备等。存储器套件通过开关或总线连接到选择性配对设施。

4. 发明授权

US08635492B2 State recovery and lockstep execution restart in a system with multiprocessor pairing 失效
标题翻译：在具有多处理器配对的系统中重新启动状态恢复和锁步执行
公开(公告)号：US08635492B2
公开(公告)日：2014-01-21
申请号：US13027932
申请日：2011-02-15
申请人： Alan Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F11/00
CPC分类号： G06F11/1658 , G06F11/1064 , G06F11/1407 , G06F11/1641 , G06F11/1679 , G06F11/203 , G06F11/2043 , G06F2201/845
摘要： System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory “nest” (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus. Each selectively paired processor core is includes a transactional execution facility, wherein the system is configured to enable processor rollback to a previous state and reinitialize lockstep execution in order to recover from an incorrect execution when an incorrect execution has been detected by the selective pairing facility.
摘要翻译：用于多处理系统的系统，方法和计算机程序产品，以提供处理器核心的选择性配对，以提高处理可靠性。提供选择性配对设施，其选择性地连接，即配对多个微处理器或处理器核，以提供一个高度可靠的线程（或线程组）。每个成对的微处理器或处理器核心提供一个高度可靠的线程，用于高可靠性与诸如存储器“嵌套”（或存储器层级），可选系统控制器和可选中断控制器的系统组件连接，可选的I / O或外设设备等。存储器套件通过开关或总线连接到选择性配对设施。每个选择性配对的处理器核心包括事务执行设施，其中所述系统被配置为使能处理器回滚到先前状态，并且重新初始化锁步执行，以便当所述选择性配对设施检测到不正确的执行时，从不正确的执行中恢复。

5. 发明授权

US08621478B2 Multiprocessor system with multiple concurrent modes of execution 有权
标题翻译：具有多个并发执行模式的多处理器系统
公开(公告)号：US08621478B2
公开(公告)日：2013-12-31
申请号：US13008502
申请日：2011-01-18
申请人： Daniel Ahn , Luis H. Ceze , Dong Chen , Alan Gara , Philip Heidelberger , Martin Ohmacht
发明人： Daniel Ahn , Luis H. Ceze , Dong Chen , Alan Gara , Philip Heidelberger , Martin Ohmacht
IPC分类号： G06F9/46
CPC分类号： G06F9/524 , G06F12/08
摘要： A multiprocessor system supports multiple concurrent modes of speculative execution. Speculation identification numbers (IDs) are allocated to speculative threads from a pool of available numbers. The pool is divided into domains, with each domain being assigned to a mode of speculation. Modes of speculation include TM, TLS, and rollback. Allocation of the IDs is carried out with respect to a central state table and using hardware pointers. The IDs are used for writing different versions of speculative results in different ways of a set in a cache memory.
摘要翻译：多处理器系统支持多种并发模式的推测执行。投机标识号（ID）从可用数字池中分配给投机线程。池被分为域，每个域被分配到一种投机模式。投机模式包括TM，TLS和回滚。对于中央状态表并使用硬件指针执行ID的分配。 ID用于以高速缓冲存储器中的集合的不同方式写入不同版本的推测结果。

6. 发明授权

US08595389B2 Distributed performance counters 失效
标题翻译：分布式性能计数器
公开(公告)号：US08595389B2
公开(公告)日：2013-11-26
申请号：US12684738
申请日：2010-01-08
申请人： Kristan D. Davis , Kahn C. Evans , Alan Gara , David L. Satterfield
发明人： Kristan D. Davis , Kahn C. Evans , Alan Gara , David L. Satterfield
IPC分类号： G06F13/00 , G06F3/00 , G06F11/00
CPC分类号： G06F13/4247 , G06F9/30145 , G06F11/3476 , G06F11/348 , G06F11/3495 , G06F12/0897 , G06F2201/88 , G06F2221/2117
摘要： A plurality of first performance counter modules is coupled to a plurality of processing cores. The plurality of first performance counter modules is operable to collect performance data associated with the plurality of processing cores respectively. A plurality of second performance counter modules are coupled to a plurality of L2 cache units, and the plurality of second performance counter modules are operable to collect performance data associated with the plurality of L2 cache units respectively. A central performance counter module may be operable to coordinate counter data from the plurality of first performance counter modules and the plurality of second performance modules, the a central performance counter module, the plurality of first performance counter modules, and the plurality of second performance counter modules connected by a daisy chain connection.
摘要翻译：多个第一性能计数器模块耦合到多个处理核心。多个第一性能计数器模块可操作以分别收集与多个处理核心相关联的性能数据。多个第二性能计数器模块耦合到多个L2高速缓存单元，并且所述多个第二性能计数器模块可操作以分别收集与所述多个L2高速缓存单元相关联的性能数据。中央性能计数器模块可以用于协调来自多个第一性能计数器模块和多个第二性能模块的计数器数据，中央性能计数器模块，多个第一性能计数器模块和多个第二性能计数器模块通过菊花链连接连接。

7. 发明授权

US08571834B2 Opcode counting for performance measurement 失效
公开(公告)号：US08571834B2
公开(公告)日：2013-10-29
申请号：US12688773
申请日：2010-01-15
申请人： Alan Gara , David L. Satterfield , Robert E. Walkup
发明人： Alan Gara , David L. Satterfield , Robert E. Walkup
IPC分类号： G21C17/00
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.

8. 发明授权

US08458684B2 Insertion of operation-and-indicate instructions for optimized SIMD code 有权
标题翻译：插入优化SIMD代码的操作和指示说明
公开(公告)号：US08458684B2
公开(公告)日：2013-06-04
申请号：US12543628
申请日：2009-08-19
申请人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind
IPC分类号： G06F9/45
CPC分类号： G06F8/451 , G06F9/30036 , G06F9/30043 , G06F9/3865 , G06F9/3887
摘要： Mechanisms are provided for inserting indicated instructions for tracking and indicating exceptions in the execution of vectorized code. A portion of first code is received for compilation. The portion of first code is analyzed to identify non-speculative instructions performing designated non-speculative operations in the first code that are candidates for replacement by replacement operation-and-indicate instructions that perform the designated non-speculative operations and further perform an indication operation for indicating any exception conditions corresponding to special exception values present in vector register inputs to the replacement operation-and-indicate instructions. The replacement is performed and second code is generated based on the replacement of the at least one non-speculative instruction. The data processing system executing the compiled code is configured to store special exception values in vector output registers, in response to a speculative instruction generating an exception condition, without initiating exception handling.
摘要翻译：提供了用于在执行向量化代码中插入指示的跟踪指示和指示异常的机制。第一个代码的一部分被接收用于编译。对第一代码的部分进行分析，以识别在第一代码中执行指定的非推测操作的非推测指令，该第一代码中的替代操作指示指令执行指定的非投机操作并进一步执行指示操作用于指示对应于向量寄存器输入中存在的替换操作和指示指令的特殊异常值的任何异常条件。执行替换，并且基于替换至少一个非推测性指令来生成第二代码。执行编译代码的数据处理系统被配置为在矢量输出寄存器中存储特殊异常值，以响应于产生异常条件的推测指令，而不启动异常处理。

9. 发明授权

US08458282B2 Extended write combining using a write continuation hint flag 失效
标题翻译：使用写入连续提示标志进行扩展写入组合
公开(公告)号：US08458282B2
公开(公告)日：2013-06-04
申请号：US11768593
申请日：2007-06-26
申请人： Dong Chen , Alan Gara , Philip Heidelberger , Martin Ohmacht , Pavlos Vranas
发明人： Dong Chen , Alan Gara , Philip Heidelberger , Martin Ohmacht , Pavlos Vranas
IPC分类号： G06F15/167 , G06F15/16 , G06F13/00 , G06F13/28
CPC分类号： H04L49/9021 , G06F12/0862 , H04L49/90
摘要： A computing apparatus for reducing the amount of processing in a network computing system which includes a network system device of a receiving node for receiving electronic messages comprising data. The electronic messages are transmitted from a sending node. The network system device determines when more data of a specific electronic message is being transmitted. A memory device stores the electronic message data and communicating with the network system device. A memory subsystem communicates with the memory device. The memory subsystem stores a portion of the electronic message when more data of the specific message will be received, and the buffer combines the portion with later received data and moves the data to the memory device for accessible storage.
摘要翻译：一种用于减少网络计算系统中的处理量的计算装置，其包括用于接收包括数据的电子消息的接收节点的网络系统设备。从发送节点发送电子消息。网络系统设备确定何时正在发送特定电子消息的更多数据。存储装置存储电子消息数据并与网络系统装置进行通信。存储器子系统与存储器件通信。当更多的特定消息的数据将被接收时，存储器子系统存储电子消息的一部分，并且缓冲器将该部分与稍后接收的数据组合，并将数据移动到存储器装置以进行存取。

10. 发明授权

US08397052B2 Version pressure feedback mechanisms for speculative versioning caches 失效
标题翻译：针对推测版本控制缓存的版本压力反馈机制
公开(公告)号：US08397052B2
公开(公告)日：2013-03-12
申请号：US12543688
申请日：2009-08-19
申请人： Alexandre E. Eichenberger , Alan Gara , Kathryn M. O'Brien , Martin Ohmacht , Xiaotong Zhuang
发明人： Alexandre E. Eichenberger , Alan Gara , Kathryn M. O'Brien , Martin Ohmacht , Xiaotong Zhuang
IPC分类号： G06F9/318
CPC分类号： G06F9/3851 , G06F9/3885 , G06F12/0842
摘要： Mechanisms are provided for controlling version pressure on a speculative versioning cache. Raw version pressure data is collected based on one or more threads accessing cache lines of the speculative versioning cache. One or more statistical measures of version pressure are generated based on the collected raw version pressure data. A determination is made as to whether one or more modifications to an operation of a data processing system are to be performed based on the one or more statistical measures of version pressure, the one or more modifications affecting version pressure exerted on the speculative versioning cache. An operation of the data processing system is modified based on the one or more determined modifications, in response to a determination that one or more modifications to the operation of the data processing system are to be performed, to affect the version pressure exerted on the speculative versioning cache.
摘要翻译：提供了用于控制推测版本缓存的版本压力的机制。基于访问推测性版本缓存的高速缓存行的一个或多个线程来收集原始版本压力数据。基于收集的原始版本压力数据生成版本压力的一个或多个统计度量。确定是否将基于版本压力的一个或多个统计测量来执行对数据处理系统的操作的一个或多个修改，该一个或多个修改影响施加在推测版本缓存上的版本压力。响应于将要执行对数据处理系统的操作的一个或多个修改以影响施加在投机上的版本压力的确定，基于一个或多个确定的修改来修改数据处理系统的操作版本缓存。

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