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61. 发明授权

US07802025B2 DMA engine for repeating communication patterns 失效
标题翻译：用于重复通信模式的DMA引擎
公开(公告)号：US07802025B2
公开(公告)日：2010-09-21
申请号：US11768795
申请日：2007-06-26
申请人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard Steinmacher-Burow , Pavlos Vranas
发明人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F15/163
摘要： A parallel computer system is constructed as a network of interconnected compute nodes to operate a global message-passing application for performing communications across the network. Each of the compute nodes includes one or more individual processors with memories which run local instances of the global message-passing application operating at each compute node to carry out local processing operations independent of processing operations carried out at other compute nodes. Each compute node also includes a DMA engine constructed to interact with the application via Injection FIFO Metadata describing multiple Injection FIFOs where each Injection FIFO may containing an arbitrary number of message descriptors in order to process messages with a fixed processing overhead irrespective of the number of message descriptors included in the Injection FIFO.
摘要翻译：并行计算机系统被构造为互连的计算节点的网络，以操作用于在整个网络上执行通信的全局消息传递应用。每个计算节点包括具有存储器的一个或多个单独处理器，该存储器运行在每个计算节点处操作的全局消息传递应用的本地实例，以独立于在其他计算节点执行的处理操作来执行本地处理操作。每个计算节点还包括构造成通过描述多个注入FIFO的注入FIFO元数据与应用交互的DMA引擎，其中每个注入FIFO可以包含任意数量的消息描述符，以便处理具有固定处理开销的消息，而不管消息的数量描述符包含在注入FIFO中。

62. 发明授权

US07486619B2 Multidimensional switch network 失效
标题翻译：多维交换机网络
公开(公告)号：US07486619B2
公开(公告)日：2009-02-03
申请号：US10793068
申请日：2004-03-04
申请人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas , Matthias Augustin Blumrich
发明人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas , Matthias Augustin Blumrich
IPC分类号： H04L12/28
CPC分类号： H04L49/1576 , H04L45/06
摘要： Multidimensional switch data networks are disclosed, such as are used by a distributed-memory parallel computer, as applied for example to computations in the field of life sciences. A distributed memory parallel computing system comprises a number of parallel compute nodes and a message passing data network connecting the compute nodes together. The data network connecting the compute nodes comprises a multidimensional switch data network of compute nodes having N dimensions, and a number/array of compute nodes Ln in each of the N dimensions. Each compute node includes an N port routing element having a port for each of the N dimensions. Each compute node of an array of Ln compute nodes in each of the N dimensions connects through a port of its routing element to an Ln port crossbar switch having Ln ports. Several embodiments are disclosed of a 4 dimensional computing system having 65,536 compute nodes.
摘要翻译：公开了多维交换机数据网络，例如由分布式存储器并行计算机使用的，例如应用于生命科学领域的计算。分布式存储器并行计算系统包括多个并行计算节点和将计算节点连接在一起的消息传递数据网络。连接计算节点的数据网络包括具有N维的计算节点的多维交换机数据网络和N个维度中的每一个中的计算节点Ln的数量/数组。每个计算节点包括具有用于N个维度中的每一个的端口的N端口路由元件。每个N维中的Ln计算节点阵列的每个计算节点通过其路由元素的端口连接到具有Ln端口的Ln端口交叉开关。公开了具有65,536个计算节点的四维计算系统的几个实施例。

63. 发明授权

US07315877B2 Efficient implementation of a multidimensional fast fourier transform on a distributed-memory parallel multi-node computer 有权
标题翻译：在分布式存储器并行多节点计算机上高效实现多维快速傅里叶变换
公开(公告)号：US07315877B2
公开(公告)日：2008-01-01
申请号：US10468998
申请日：2002-02-25
申请人： Gyan V. Bhanot , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas
发明人： Gyan V. Bhanot , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard D. Steinmacher-Burow , Pavlos M. Vranas
IPC分类号： G06F17/14
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： The present in invention is directed to a method, system and program storage device for efficiently implementing a multidimensional Fast Fourier Transform (FFT) of a multidimensional array comprising a plurality of elements initially distributed in a multi-node computer system comprising a plurality of nodes in communication over a network, comprising: distributing the plurality of elements of the array in a first dimension across the plurality of nodes of the computer system over the network to facilitate a first one-dimensional FFT; performing the first one-dimensional FFT on the elements of the array distributed at each node in the first dimension; re-distributing the one-dimensional FFT-transformed elements at each node in a second dimension via “all-to-all” distribution in random order across other nodes of the computer system over the network; and performing a second one-dimensional FFT on elements of the array re-distributed at each node in the second dimension, wherein the random order facilitates efficient utilization of the network thereby efficiently implementing the multidimensional FFT. The “all-to-all” re-distribution of array elements is further efficiently implemented in applications other than the multidimensional FFT on the distributed-memory parallel supercomputer.
摘要翻译：发明内容涉及一种用于有效地实现多维阵列的多维快速傅里叶变换（FFT）的方法，系统和程序存储设备，所述多维阵列包括最初分布在多节点计算机系统中的多个元素，所述多节点包括多个节点通过网络进行通信，包括：通过所述网络在所述计算机系统的所述多个节点之间以第一维度分布所述阵列的所述多个元素以促进第一一维FFT; 对分布在第一维度中的每个节点的阵列的元素执行第一个一维FFT; 通过网络上的计算机系统的其他节点以随机顺序的“全对全”分布，在第二维度中的每个节点处重新分布一维FFT变换的元素; 以及对在所述第二维度中的每个节点处重新分布的阵列的元素执行第二一维FFT，其中所述随机顺序有助于所述网络的有效利用，从而有效地实现所述多维FFT。在分布式存储器并行超级计算机上的多维FFT以外的应用中，数组元素的“全部”重新分配进一步有效地实现。

64. 发明授权

US07210088B2 Fault isolation through no-overhead link level CRC 失效
标题翻译：通过无架空链路级CRC进行故障隔离
公开(公告)号：US07210088B2
公开(公告)日：2007-04-24
申请号：US10468996
申请日：2002-02-25
申请人： Dong Chen , Paul W. Coteus , Alan G. Gara
发明人： Dong Chen , Paul W. Coteus , Alan G. Gara
IPC分类号： G06F11/00 , G06F13/00 , G06F7/02 , H03M13/00
CPC分类号： H03M13/091 , G11B20/1833 , H04L1/0061
摘要： A fault isolation technique for checking the accuracy of data packets transmitted between nodes of a parallel processor. An independent crc is kept of all data sent from one processor to another, and received from one processor to another. At the end of each checkpoint, the crcs are compared. If they do not match, there was an error. The crcs may be cleared and restarted at each checkpoint. In the preferred embodiment, the basic functionality is to calculate a CRC of all packet data that has been successfully transmitted across a given link. This CRC is done on both ends of the link, thereby allowing an independent check on all data believed to have been correctly transmitted. Preferably, all links have this CRC coverage, and the CRC used in this link level check is different from that used in the packet transfer protocol. This independent check, if successfully passed, virtually eliminates the possibility that any data errors were missed during the previous transfer period.
摘要翻译：用于检查并行处理器节点之间传输的数据包的精度的故障隔离技术。保持从一个处理器发送到另一个处理器的所有数据的独立crc，并从一个处理器接收另一个处理器。在每个检查点的末尾，比较crcs。如果它们不匹配，则出现错误。可以在每个检查点清除并重新启动crcs。在优选实施例中，基本功能是计算已经通过给定链路成功发送的所有分组数据的CRC。该CRC在链路的两端完成，从而允许对所有被认为已被正确发送的数据进行独立的检查。优选地，所有链路具有该CRC覆盖，并且在该链路级检查中使用的CRC与在分组传送协议中使用的不同。这种独立检查，如果成功通过，几乎消除了在以前的传输期间错过任何数据错误的可能性。

65. 发明授权

US08010875B2 Error correcting code with chip kill capability and power saving enhancement 有权
标题翻译：错误纠正代码具有芯片杀死能力和节能增强
公开(公告)号：US08010875B2
公开(公告)日：2011-08-30
申请号：US11768559
申请日：2007-06-26
申请人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
发明人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
IPC分类号： G06F11/10
CPC分类号： G06F11/1012
摘要： A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.
摘要翻译：公开了一种用于检测计算机存储器系统中的存储器芯片故障的方法和系统。该方法包括以下步骤：从一组用户数据芯片访问用户数据，以及使用来自一组系统数据芯片的数据来测试用户数据的错误。该测试通过从用户数据生成检查符号序列来完成，将用户数据分组成数据符号序列，并计算指定的综合征序列。如果所有的综合征为零，则用户数据没有错误。如果其中一个校正子不为零，则计算一组鉴别符表达式，并用于确定是否发生单个或双重符号错误。在优选实施例中，使用少于两个全系统数据芯片来测试和校正用户数据。

66. 发明申请

US20090006899A1 ERROR CORRECTING CODE WITH CHIP KILL CAPABILITY AND POWER SAVING ENHANCEMENT 有权
标题翻译：错误修正代码与芯片杀伤能力和省电增强
公开(公告)号：US20090006899A1
公开(公告)日：2009-01-01
申请号：US11768559
申请日：2007-06-26
申请人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
发明人： Alan G. Gara , Dong Chen , Paul W. Coteus , William T. Flynn , James A. Marcella , Todd Takken , Barry M. Trager , Shmuel Winograd
IPC分类号： G06F11/26 , G06F11/16
CPC分类号： G06F11/1012
摘要： A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.
摘要翻译：公开了一种用于检测计算机存储器系统中的存储器芯片故障的方法和系统。该方法包括以下步骤：从一组用户数据芯片访问用户数据，以及使用来自一组系统数据芯片的数据来测试用户数据的错误。该测试通过从用户数据生成检查符号序列来完成，将用户数据分组成数据符号序列，并计算指定的综合征序列。如果所有的综合征为零，则用户数据没有错误。如果其中一个校正子不为零，则计算一组鉴别符表达式，并用于确定是否发生单个或双重符号错误。在优选实施例中，使用少于两个全系统数据芯片来测试和校正用户数据。

67. 发明授权

US08412974B2 Global synchronization of parallel processors using clock pulse width modulation 有权
标题翻译：使用时钟脉宽调制的并行处理器的全局同步
公开(公告)号：US08412974B2
公开(公告)日：2013-04-02
申请号：US12696764
申请日：2010-01-29
申请人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
发明人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
IPC分类号： G06F1/04 , G06F1/12 , G06F15/16
CPC分类号： G06F1/08 , G06F1/10
摘要： A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
摘要翻译：电路产生具有脉冲宽度修改的全局时钟信号，以使并行计算系统中的处理器同步。电路可以包括硬件模块和时钟分离器。硬件模块可以产生时钟信号并对时钟信号进行脉冲宽度修改。脉冲宽度修改在时钟信号的时钟周期内改变脉冲宽度。时钟分配器可以将脉冲宽度修改的时钟信号分配给并行计算系统中的多个处理器。

68. 发明申请

US20110119475A1 GLOBAL SYNCHRONIZATION OF PARALLEL PROCESSORS USING CLOCK PULSE WIDTH MODULATION 有权
标题翻译：使用时钟脉冲宽度调制的并行处理器的全局同步
公开(公告)号：US20110119475A1
公开(公告)日：2011-05-19
申请号：US12696764
申请日：2010-01-29
申请人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
发明人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
IPC分类号： G06F1/12 , G06F1/10 , G06F9/00 , G06F1/08
CPC分类号： G06F1/08 , G06F1/10
摘要： A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
摘要翻译：电路产生具有脉冲宽度修改的全局时钟信号，以使并行计算系统中的处理器同步。电路可以包括硬件模块和时钟分离器。硬件模块可以产生时钟信号并对时钟信号进行脉冲宽度修改。脉冲宽度修改在时钟信号的时钟周期内改变脉冲宽度。时钟分配器可以将脉冲宽度修改的时钟信号分配给并行计算系统中的多个处理器。

69. 发明授权

US07418068B2 Data capture technique for high speed signaling 失效
标题翻译：高速信号数据采集技术
公开(公告)号：US07418068B2
公开(公告)日：2008-08-26
申请号：US10468992
申请日：2002-02-25
申请人： Wayne Melvin Barrett , Dong Chen , Paul William Coteus , Alan Gene Gara , Rory Jackson , Gerard Vincent Kopcsay , Ben Jesse Nathanson , Paylos Michael Vranas , Todd E. Takken
发明人： Wayne Melvin Barrett , Dong Chen , Paul William Coteus , Alan Gene Gara , Rory Jackson , Gerard Vincent Kopcsay , Ben Jesse Nathanson , Paylos Michael Vranas , Todd E. Takken
IPC分类号： H04L7/00
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.
摘要翻译：用于高速信令的数据捕获技术，以允许异步数据流的最佳采样。这种技术允许极高的数据速率，并且不要求在源同步系统中进行数据发送时钟。本发明还提供了用于自动调整用于最佳两比特双向（SiBiDi）信令的传输延迟的硬件机制。

70. 发明授权

US09507647B2 Cache as point of coherence in multiprocessor system 有权
标题翻译：缓存作为多处理器系统中的一致性点
公开(公告)号：US09507647B2
公开(公告)日：2016-11-29
申请号：US13008531
申请日：2011-01-18
申请人： Matthias A. Blumrich , Luis H. Ceze , Dong Chen , Alan Gara , Phlip Heidelberger , Martin Ohmacht , Burkhard Steinmacher-Burow , Xiaotong Zhuang
发明人： Matthias A. Blumrich , Luis H. Ceze , Dong Chen , Alan Gara , Phlip Heidelberger , Martin Ohmacht , Burkhard Steinmacher-Burow , Xiaotong Zhuang
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/52 , G06F12/08
CPC分类号： G06F9/524 , G06F12/08
摘要： In a multiprocessor system, a conflict checking mechanism is implemented in the L2 cache memory. Different versions of speculative writes are maintained in different ways of the cache. A record of speculative writes is maintained in the cache directory. Conflict checking occurs as part of directory lookup. Speculative versions that do not conflict are aggregated into an aggregated version in a different way of the cache. Speculative memory access requests do not go to main memory.
摘要翻译：在多处理器系统中，在L2高速缓冲存储器中实现冲突检查机制。不同版本的推测性写入以不同的方式保存在缓存中。高速缓存目录中保留了推测性写入记录。冲突检查作为目录查找的一部分发生。不冲突的推测版本以不同的缓存方式聚合成聚合版本。推测内存访问请求不会转到主内存。

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