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1. 发明授权

US07426672B2 Method for implementing processor bus speculative data completion 失效
标题翻译：实现处理器总线推测数据完成的方法
公开(公告)号：US07426672B2
公开(公告)日：2008-09-16
申请号：US11116624
申请日：2005-04-28
申请人： Wayne Melvin Barrett , Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Wayne Melvin Barrett , Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： H03M13/00
CPC分类号： G06F11/10
摘要： A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.
摘要翻译：提供了一种用于在计算机系统中实现处理器总线推测数据完成的方法和装置。计算机系统中的存储器控制器将未校正的数据从存储器发送到处理器总线。存储器控制器还将未校正的数据应用于纠错码（ECC）校验和校正电路。当检测到单个位错误（SBE）时，校正的数据在未校正的数据之后被发送到处理器总线预定数量的周期。

2. 发明申请

US20080222489A1 APPARATUS FOR IMPLEMENTING PROCESSOR BUS SPECULATIVE DATA COMPLETION 失效
标题翻译：执行处理器总线测量数据完成的装置
公开(公告)号：US20080222489A1
公开(公告)日：2008-09-11
申请号：US12127118
申请日：2008-05-27
申请人： Wayne Melvin Barrett , Philip Rogers Hillier , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Wayne Melvin Barrett , Philip Rogers Hillier , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： G06F11/10
CPC分类号： G06F11/10
摘要： A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.
摘要翻译：提供了一种用于在计算机系统中实现处理器总线推测数据完成的方法和装置。计算机系统中的存储器控制器将未校正的数据从存储器发送到处理器总线。存储器控制器还将未校正的数据应用于纠错码（ECC）校验和校正电路。当检测到单个位错误（SBE）时，校正的数据在未校正的数据之后被发送到处理器总线预定数量的周期。

3. 发明授权

US08804960B2 Implementing known scrambling relationship among multiple serial links 有权
标题翻译：在多个串行链路之间实现已知的加扰关系
公开(公告)号：US08804960B2
公开(公告)日：2014-08-12
申请号：US12709662
申请日：2010-02-22
申请人： Wayne Melvin Barrett , Kenneth Michael Valk
发明人： Wayne Melvin Barrett , Kenneth Michael Valk
IPC分类号： H04L9/12 , H04L29/06 , G06F13/00
CPC分类号： H04L63/0457 , G06F1/12 , G06F13/00 , H04L2209/12
摘要： A method and circuit for implementing known scrambling relationship among multiple serial links, and a design structure on which the subject circuit resides are provided. A transmit Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for scrambling transmitted data. A receive Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for descrambling received data. Each of the transmit LFSRs is initialized to a unique value. Each transmit LFSR conveys a current unique value to a receive LFSR for synchronizing the transmit LFSR and receive LFSR to begin scrambling and descrambling data.
摘要翻译：一种用于实现多个串行链路之间的已知加扰关系的方法和电路，以及设置有该主题电路所在的设计结构。发送线性反馈移位寄存器（LFSR）与多个串行链路中的每一个一起提供，用于加扰发送的数据。每个多个串行链路提供接收线性反馈移位寄存器（LFSR），用于解扰接收到的数据。每个发送LFSR被初始化为唯一值。每个发送的LFSR向接收LFSR传送当前唯一的值以使发送LFSR同步并且接收LFSR以开始加扰和解扰数据。

4. 发明申请

US20110208954A1 IMPLEMENTING KNOWN SCRAMBLING RELATIONSHIP AMONG MULTIPLE SERIAL LINKS 有权
标题翻译：在多个串行链路上实现已知的屏蔽关系
公开(公告)号：US20110208954A1
公开(公告)日：2011-08-25
申请号：US12709662
申请日：2010-02-22
申请人： Wayne Melvin Barrett , Kenneth Michael Valk
发明人： Wayne Melvin Barrett , Kenneth Michael Valk
IPC分类号： G06F12/14 , G06F9/24 , G06F1/12
CPC分类号： H04L63/0457 , G06F1/12 , G06F13/00 , H04L2209/12
摘要： A method and circuit for implementing known scrambling relationship among multiple serial links, and a design structure on which the subject circuit resides are provided. A transmit Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for scrambling transmitted data. A receive Linear Feedback Shift Register (LFSR) is provided with each of the multiple serial links for descrambling received data. Each of the transmit LFSRs is initialized to a unique value. Each transmit LFSR conveys a current unique value to a receive LFSR for synchronizing the transmit LFSR and receive LFSR to begin scrambling and descrambling data.
摘要翻译：一种用于实现多个串行链路之间的已知加扰关系的方法和电路，以及设置有该主题电路所在的设计结构。发送线性反馈移位寄存器（LFSR）与多个串行链路中的每一个一起提供，用于加扰发送的数据。每个多个串行链路提供接收线性反馈移位寄存器（LFSR），用于解扰接收到的数据。每个发送LFSR被初始化为唯一值。每个发送的LFSR向接收LFSR传送当前唯一的值以使发送LFSR同步并且接收LFSR以开始加扰和解扰数据。

5. 发明申请

US20110206141A1 IMPLEMENTING SERIAL LINK TRAINING PATTERNS SEPARATED BY RANDOM DATA 有权
标题翻译：实现随机数据分离的串行链接训练模式
公开(公告)号：US20110206141A1
公开(公告)日：2011-08-25
申请号：US12709733
申请日：2010-02-22
申请人： Wayne Melvin Barrett , Kenneth Michael Valk
发明人： Wayne Melvin Barrett , Kenneth Michael Valk
IPC分类号： H04L27/00
CPC分类号： H04L5/1438
摘要： A method and circuit for implementing serial link training sequences, and a design structure on which the subject circuit resides are provided. A transmitter device transmits a training sequence (TS) pattern; then the transmitter device transmits random data for a predefined time duration. The steps of transmitting the TS-pattern, then transmitting the random data for the fixed time duration are repeated. A receiver device detecting a plurality of the TS-patterns separated by the predefined time interval of random data, performs receiver initialization steps. The receiver device performs a plurality of receiver initialization steps including, for example, acquiring byte lock, and a link width determination.
摘要翻译：一种用于实现串行链路训练序列的方法和电路，以及设置该对象电路所在的设计结构。发射机设备发送训练序列（TS）模式; 则发射机设备在预定义的持续时间内发送随机数据。重复发送TS模式，然后发送固定持续时间的随机数据的步骤。检测分离了随机数据的预定时间间隔的多个TS模式的接收机设备执行接收机初始化步骤。接收机装置执行多个接收机初始化步骤，包括例如获取字节锁定和链路宽度确定。

6. 发明申请

US20090028073A1 DATA CAPTURE TECHNIQUE FOR HGH SPEED SIGNALING 有权
标题翻译： HGH速度信号的数据采集技术
公开(公告)号：US20090028073A1
公开(公告)日：2009-01-29
申请号：US12191893
申请日：2008-08-14
申请人： Wayne Melvin Barrett , Dong Chen , Paul William Coteus , Alan Gene Gara , Rory Jackson , Gerard Vincent Kopcsay , Ben Jesse Nathanson , Pavlos Michael Vranas
发明人： Wayne Melvin Barrett , Dong Chen , Paul William Coteus , Alan Gene Gara , Rory Jackson , Gerard Vincent Kopcsay , Ben Jesse Nathanson , Pavlos Michael Vranas
IPC分类号： H04L5/14
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.
摘要翻译：用于高速信令的数据捕获技术，以允许异步数据流的最佳采样。这种技术允许极高的数据速率，并且不要求在源同步系统中进行数据发送时钟。本发明还提供了用于自动调整用于最佳两比特双向（SiBiDi）信令的传输延迟的硬件机制。

7. 发明授权

US06185646B2 Method and apparatus for transferring data on a synchronous multi-drop 失效
标题翻译：用于在同步多点传送数据的方法和装置
公开(公告)号：US06185646B2
公开(公告)日：2001-02-06
申请号：US08984611
申请日：1997-12-03
申请人： Wayne Melvin Barrett , Gerald Keith Bartley , Douglas A. Baska , Paul Eric Dahlen , Robert Allen Drehmel , Kenneth Claude Hinz , James Anthony Marcella
发明人： Wayne Melvin Barrett , Gerald Keith Bartley , Douglas A. Baska , Paul Eric Dahlen , Robert Allen Drehmel , Kenneth Claude Hinz , James Anthony Marcella
IPC分类号： G06F1300
CPC分类号： G06F13/1663
摘要： A data transfer method and apparatus are provided for transferring data in a computer system on a high-speed synchronous multi-drop bus. Multiple devices including at least a first group of a plurality of devices and a second group of at least one device are connected to the high-speed synchronous multi-drop bus. To transfer data between devices in the first group, a first unidirectional data valid signal is applied to each device in the second group. The data from a sending device in the first group is transferred to a designated device in the second group. A second unidirectional data valid signal is applied to each device in the first group. The data is transferred from the designated device in the second group to a selected device in the first group.
摘要翻译：提供了一种用于在高速同步多点总线上的计算机系统中传送数据的数据传送方法和装置。包括至少第一组多个设备的多个设备和至少一个设备的第二组连接到高速同步多点总线。为了在第一组中的设备之间传输数据，第一组中的每个设备应用第一单向数据有效信号。来自第一组中的发送设备的数据被传送到第二组中的指定设备。对第一组中的每个设备应用第二单向数据有效信号。数据从第二组中的指定设备传送到第一组中的所选设备。

8. 发明授权

US08275922B2 Implementing serial link training patterns separated by random data for training a serial link in an interconnect system 有权
标题翻译：实现由随机数据分离的串行链路训练模式，用于训练互连系统中的串行链路
公开(公告)号：US08275922B2
公开(公告)日：2012-09-25
申请号：US12709733
申请日：2010-02-22
申请人： Wayne Melvin Barrett , Kenneth Michael Valk
发明人： Wayne Melvin Barrett , Kenneth Michael Valk
IPC分类号： G06F13/42
CPC分类号： H04L5/1438
摘要： A method and circuit for implementing serial link training sequences, and a design structure on which the subject circuit resides are provided. A transmitter device transmits a training sequence (TS) pattern; then the transmitter device transmits random data for a predefined time duration. The steps of transmitting the TS-pattern, then transmitting the random data for the fixed time duration are repeated. A receiver device detecting a plurality of the TS-patterns separated by the predefined time interval of random data, performs receiver initialization steps. The receiver device performs a plurality of receiver initialization steps including, for example, acquiring byte lock, and a link width determination.
摘要翻译：一种用于实现串行链路训练序列的方法和电路，以及设置该对象电路所在的设计结构。发射机设备发送训练序列（TS）模式; 则发射机设备在预定义的持续时间内发送随机数据。重复发送TS模式，然后发送固定持续时间的随机数据的步骤。检测分离了随机数据的预定时间间隔的多个TS模式的接收机设备执行接收机初始化步骤。接收机装置执行多个接收机初始化步骤，包括例如获取字节锁定和链路宽度确定。

9. 发明授权

US07392353B2 Prioritization of out-of-order data transfers on shared data bus 有权
标题翻译：共享数据总线上无序数据传输的优先级
公开(公告)号：US07392353B2
公开(公告)日：2008-06-24
申请号：US11004199
申请日：2004-12-03
申请人： Wayne Melvin Barrett , Brian T. Vanderpool
发明人： Wayne Melvin Barrett , Brian T. Vanderpool
IPC分类号： G06F13/18 , G06F9/312
CPC分类号： G06F13/1626
摘要： Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.
摘要翻译：无条件优先级被提供给由多个存储器请求者共享的数据总线上的按顺序数据传输的无序数据传输。通过总是优先处理诸如写入和/或缓存到高速缓存数据传输之类的按顺序传输的延迟读取数据传输的无序传输，确保没有较新的命令或事务对延迟产生负面影响的旧命令或事务。

10. 发明授权

US08103930B2 Apparatus for implementing processor bus speculative data completion 失效
标题翻译：用于实现处理器总线推测数据完成的装置
公开(公告)号：US08103930B2
公开(公告)日：2012-01-24
申请号：US12127118
申请日：2008-05-27
申请人： Wayne Melvin Barrett , Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
发明人： Wayne Melvin Barrett , Philip Rogers Hillier, III , Joseph Allen Kirscht , Elizabeth A. McGlone
IPC分类号： H03M13/00
CPC分类号： G06F11/10
摘要： A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.
摘要翻译：提供了一种用于在计算机系统中实现处理器总线推测数据完成的方法和装置。计算机系统中的存储器控制器将未校正的数据从存储器发送到处理器总线。存储器控制器还将未校正的数据应用于纠错码（ECC）校验和校正电路。当检测到单个位错误（SBE）时，校正的数据在未校正的数据之后被发送到处理器总线预定数量的周期。

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