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1. 发明授权

US08412974B2 Global synchronization of parallel processors using clock pulse width modulation 有权
标题翻译：使用时钟脉宽调制的并行处理器的全局同步
公开(公告)号：US08412974B2
公开(公告)日：2013-04-02
申请号：US12696764
申请日：2010-01-29
申请人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
发明人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
IPC分类号： G06F1/04 , G06F1/12 , G06F15/16
CPC分类号： G06F1/08 , G06F1/10
摘要： A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
摘要翻译：电路产生具有脉冲宽度修改的全局时钟信号，以使并行计算系统中的处理器同步。电路可以包括硬件模块和时钟分离器。硬件模块可以产生时钟信号并对时钟信号进行脉冲宽度修改。脉冲宽度修改在时钟信号的时钟周期内改变脉冲宽度。时钟分配器可以将脉冲宽度修改的时钟信号分配给并行计算系统中的多个处理器。

2. 发明申请

US20110119475A1 GLOBAL SYNCHRONIZATION OF PARALLEL PROCESSORS USING CLOCK PULSE WIDTH MODULATION 有权
标题翻译：使用时钟脉冲宽度调制的并行处理器的全局同步
公开(公告)号：US20110119475A1
公开(公告)日：2011-05-19
申请号：US12696764
申请日：2010-01-29
申请人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
发明人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
IPC分类号： G06F1/12 , G06F1/10 , G06F9/00 , G06F1/08
CPC分类号： G06F1/08 , G06F1/10
摘要： A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
摘要翻译：电路产生具有脉冲宽度修改的全局时钟信号，以使并行计算系统中的处理器同步。电路可以包括硬件模块和时钟分离器。硬件模块可以产生时钟信号并对时钟信号进行脉冲宽度修改。脉冲宽度修改在时钟信号的时钟周期内改变脉冲宽度。时钟分配器可以将脉冲宽度修改的时钟信号分配给并行计算系统中的多个处理器。

3. 发明申请

US20090063894A1 Autonomic PCI Express Hardware Detection and Failover Mechanism 审中-公开
标题翻译：自动PCI Express硬件检测和故障转移机制
公开(公告)号：US20090063894A1
公开(公告)日：2009-03-05
申请号：US11846783
申请日：2007-08-29
申请人： Ronald L. Billau , John D. Folkerts , Ross L. Franke , James S. Harveland , Brian G. Holthaus
发明人： Ronald L. Billau , John D. Folkerts , Ross L. Franke , James S. Harveland , Brian G. Holthaus
IPC分类号： G06F11/07 , G06F13/00 , G06F13/14
CPC分类号： G06F13/4282 , G06F11/2005 , G06F2213/0026
摘要： A system with an autonomic PCI Express hardware detection and failover mechanism includes a plurality of combination root complex capable and endpoint capable devices. A combination root complex capable and endpoint capable device may be selectively configured to operate in either a root complex mode or an endpoint mode. One of the devices assumes the root complex mode and the remaining devices each assume the endpoint mode. Each of the endpoint mode devices is adapted to detect a failure of the root complex mode device. In response to detection of the failure of the root complex mode device, one of the endpoint mode devices assumes root complex mode. An endpoint device may include a timer with a timeout value. Whenever, an endpoint device receives a communication from the root complex device, the endpoint device restarts its timer. If the timer times out with the endpoint device receiving a communication from the root complex device, the endpoint device issues a read request to the root complex device. If the root complex device does not respond to the read request, the endpoint device assumes root complex mode. Different endpoint devices may be assigned different timeout values. Accordingly, the endpoint device that is assigned the shortest time out value will assume root complex mode upon detection of a root complex device failure.
摘要翻译：具有自主PCI Express硬件检测和故障转移机制的系统包括多个具有组合根复合能力和端点能力的设备。可以选择性地将具有能力和端点的组合的根复合能力设备配置为在根复合模式或端点模式中操作。其中一个设备假定根复合模式，其余的设备都采用端点模式。端点模式设备中的每一个适于检测根复合模式设备的故障。响应于检测到根复杂模式设备的故障，端点模式设备之一呈现根复合模式。端点设备可以包括具有超时值的定时器。每当端点设备从根复杂设备接收到通信时，端点设备重启其定时器。如果定时器超时，端点设备从根复杂设备接收通信，则端点设备向根配置设备发出读请求。如果根配置设备不响应读请求，则端点设备将采用根复合模式。可以为不同的端点设备分配不同的超时值。因此，在检测到根复杂设备故障时，分配有最短超时值的端点设备将呈现根复合模式。

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