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51. 发明授权

US06643557B1 Method and apparatus for using scatterometry to perform feedback and feed-forward control 有权
标题翻译：使用散射法进行反馈和前馈控制的方法和装置
公开(公告)号：US06643557B1
公开(公告)日：2003-11-04
申请号：US09591038
申请日：2000-06-09
申请人： Michael L. Miller , Anthony J. Toprac
发明人： Michael L. Miller , Anthony J. Toprac
IPC分类号： G06F1900
CPC分类号： H01L22/26
摘要： The present invention provides for a method and an apparatus for using scatterometry to perform feedback and feed-forward control. A processing run of semiconductor devices is performed. Metrology data from the processed semiconductor devices is acquired. Error data is acquired by analyzing the acquired metrology data. A determination is made whether the error data merits modification to the processing of semiconductor devices. A feedback modification of the processing of semiconductor devices is performed in response to the determination that the error data merits modification to the processing of semiconductor devices. A feed-forward modification of the processing of the semiconductor devices is performed in response to the determination that the error data merits modification to the processing of semiconductor devices.
摘要翻译：本发明提供了一种使用散射测量来执行反馈和前馈控制的方法和装置。执行半导体器件的处理运行。获取来自处理的半导体器件的计量数据。通过分析获取的测量数据获取误差数据。确定误差数据是否优于对半导体器件的处理的修改。响应于确定误差数据优于对半导体器件的处理的修改，执行半导体器件的处理的反馈修改。响应于确定误差数据优于对半导体器件的处理的修改，执行半导体器件的处理的前馈修改。

52. 发明授权

US06560503B1 Method and apparatus for monitoring controller performance using statistical process control 失效
标题翻译：使用统计过程控制监控控制器性能的方法和装置
公开(公告)号：US06560503B1
公开(公告)日：2003-05-06
申请号：US09412679
申请日：1999-10-05
申请人： Anthony J. Toprac , William J. Campbell
发明人： Anthony J. Toprac , William J. Campbell
IPC分类号： G06F1900
CPC分类号： G05B19/41885 , G05B19/41875 , G05B2219/32017 , G05B2219/32191 , G05B2219/32201 , G05B2219/42001 , Y02P90/22 , Y02P90/26
摘要： The present invention provides for a method and an apparatus for monitoring controller performance using statistical process control analysis. A manufacturing model is defined. A processing run of semiconductor devices is performed as defined by the manufacturing model and implemented by a process controller. A fault detection analysis is performed on the process controller. At least one control input signal generated by the process controller is updated. The apparatus of the present invention comprises: a processing controller; a processing tool coupled with the processing controller; a metrology tool interfaced with the processing tool; a control modification data calculation unit interfaced with the metrology and connected to the processing controller in a feedback manner; a predictor function interfaced with the processing controller; an statistical process control analysis unit interfaced with the predictor function and the processing tool; and a results versus prediction analysis unit interfaced with the statistical process control analysis unit and connected to the processing controller in a feedback manner.
摘要翻译：本发明提供一种使用统计过程控制分析来监视控制器性能的方法和装置。定义了一个制造模型。半导体器件的处理运行由制造模型定义并由过程控制器实现。对过程控制器进行故障检测分析。由过程控制器生成的至少一个控制输入信号被更新。本发明的装置包括：处理控制器; 与处理控制器耦合的处理工具; 与加工工具接口的计量工具; 控制修改数据计算单元，与测量接口并以反馈方式连接到处理控制器; 与处理控制器接口的预测器功能; 与预测器功能和处理工具接口的统计过程控制分析单元; 以及与统计过程控制分析单元连接并以反馈方式连接到处理控制器的结果与预测分析单元。

53. 发明授权

US06540591B1 Method and apparatus for post-polish thickness and uniformity control 失效
标题翻译：后抛光厚度和均匀度控制的方法和装置
公开(公告)号：US06540591B1
公开(公告)日：2003-04-01
申请号：US09837606
申请日：2001-04-18
申请人： Alexander J. Pasadyn , Christopher H. Raeder , Anthony J. Toprac
发明人： Alexander J. Pasadyn , Christopher H. Raeder , Anthony J. Toprac
IPC分类号： B24B100
CPC分类号： B24B37/013 , B24B21/10 , B24B37/042 , B24B49/04
摘要： A method for polishing wafers includes providing a wafer having a process layer formed thereon; providing a polishing tool having a plurality of control zones and being adapted to polish the process layer based on an operating recipe, the operating recipe having a control variable corresponding to each of the control zones; measuring a pre-polish thickness profile of the process layer; comparing the pre-polish thickness profile to a target thickness profile to determine a desired removal profile; determining values for the control variables associated with the control zones based on the desired removal profile; and modifying the operating recipe of the polishing tool based on the values determined for the control variables. A processing line includes a polishing tool, a metrology tool, and a process controller. The polishing tool is adapted to polish a wafer having a process layer formed thereon based on an operating recipe. The polishing tool includes a plurality of control zones and the operating recipe includes a control variable corresponding to each of the control zones. The metrology tool is adapted to measure a pre-polish thickness profile of the process layer. The process controller is adapted to compare the pre-polish thickness profile to a target thickness profile to determine a desired removal profile, determine values for the control variables associated with the control zones based on the desired removal profile, and modify the operating recipe of the polishing tool based on the values determined for the control variables.
摘要翻译：抛光晶片的方法包括提供其上形成有工艺层的晶片; 提供具有多个控制区域并且适于基于操作配方抛光所述处理层的抛光工具，所述操作配方具有对应于每个所述控制区域的控制变量; 测量处理层的预抛光厚度轮廓; 将预抛光厚度轮廓与目标厚度轮廓进行比较以确定期望的移除轮廓; 基于期望的移除轮廓来确定与控制区域相关联的控制变量的值; 并且基于为控制变量确定的值来修改抛光工具的操作配方。处理线包括抛光工具，计量工具和过程控制器。抛光工具适于基于操作配方抛光其上形成有工艺层的晶片。抛光工具包括多个控制区，操作配方包括对应于每个控制区的控制变量。测量工具适用于测量工艺层的预抛光厚度轮廓。过程控制器适于将预抛光厚度分布与目标厚度分布进行比较以确定期望的去除曲线，基于期望的去除曲线来确定与控制区域相关联的控制变量的值，并修改其中的操作配方基于为控制变量确定的值的抛光工具。

54. 发明授权

US06427093B1 Method and apparatus for optimal wafer-by-wafer processing 失效
标题翻译：用于最佳晶片处理的方法和装置
公开(公告)号：US06427093B1
公开(公告)日：2002-07-30
申请号：US09414107
申请日：1999-10-07
申请人： Anthony J. Toprac
发明人： Anthony J. Toprac
IPC分类号： G06F1900
CPC分类号： H01L21/67276 , G05B19/41865 , G05B2219/32077 , G05B2219/45031 , G06Q10/06 , Y02P90/20 , Y02P90/22
摘要： The present invention provides for a method and an apparatus for optimal wafer-by-wafer processing. Semiconductor devices are identified for wafer-by-wafer analysis. At least one value of a controlled variable in the wafer-by-wafer analysis is identified. A trajectory of recipes is created for the identified semiconductor devices. A feedback implementation of wafer-by-wafer control is performed using the trajectory of recipes upon the identified semiconductor devices. A feed-forward implementation of wafer-by-wafer control is performed using the trajectory of recipes upon the identified semiconductor devices.
摘要翻译：本发明提供一种用于最佳晶片处理的方法和装置。识别半导体器件用于逐晶片分析。识别晶片分析中的受控变量的至少一个值。为识别的半导体器件创建配方轨迹。使用所识别的半导体器件上的配方的轨迹来执行逐晶片控制的反馈实现。使用所识别的半导体器件上的配方的轨迹来执行晶片间晶片控制的前馈实现。

55. 发明授权

US06405144B1 Method and apparatus for programmed latency for improving wafer-to-wafer uniformity 有权
标题翻译：用于改善晶片到晶片均匀性的编程延迟的方法和装置
公开(公告)号：US06405144B1
公开(公告)日：2002-06-11
申请号：US09484602
申请日：2000-01-18
申请人： Anthony J. Toprac , Paul Ackmann , Stuart E. Brown
发明人： Anthony J. Toprac , Paul Ackmann , Stuart E. Brown
IPC分类号： G01R3126
CPC分类号： H01L22/20
摘要： The present invention provides for a method and an apparatus for implementing programmed latency for improved wafer-to-wafer uniformity. Semiconductor devices for wafer-by-wafer analysis are identified. At least one value of a controlled variable in the wafer-by-wafer analysis is identified. A trajectory of recipes for the identified semiconductor devices is created. A sequence analysis of wafer-to-wafer variations is performed using the trajectory of recipes upon the identified semiconductor devices. A latency control is performed in response to the sequence analysis. A feed-forward implementation of wafer-by-wafer latency control is performed using the trajectory of recipes upon the identified semiconductor devices.
摘要翻译：本发明提供一种用于实现编程延迟的方法和装置，用于改善晶片到晶片的均匀性。识别用于晶片分析的半导体器件。识别晶片分析中的受控变量的至少一个值。创建了用于识别的半导体器件的配方的轨迹。使用所识别的半导体器件上的配方的轨迹来执行晶片到晶片变化的序列分析。响应于序列分析执行延迟控制。使用所识别的半导体器件上的配方的轨迹来执行逐晶片延迟控制的前馈实施。

56. 发明授权

US06368883B1 Method for identifying and controlling impact of ambient conditions on photolithography processes 有权
标题翻译：识别和控制环境条件对光刻工艺的影响的方法
公开(公告)号：US06368883B1
公开(公告)日：2002-04-09
申请号：US09371561
申请日：1999-08-10
申请人： Christopher A. Bode , Anthony J. Toprac
发明人： Christopher A. Bode , Anthony J. Toprac
IPC分类号： H01L2166
CPC分类号： G03F7/705 , G03F7/70525 , G03F7/70858 , H01L22/26
摘要： The invention is, in its various aspects, a method and apparatus for processing a semiconductor wafer. More particularly, the invention is a method and apparatus for identifying and controlling the impact of ambient conditions on photolithography processes. In a first aspect, the invention is a method for processing a semiconductor wafer. The method comprises identifying a disturbance in a photolithographic process arising from an ambient condition; modeling the identified disturbance; and applying the model to modify a control input parameter. In a second aspect, the invention is an apparatus for controlling a photolithography process. The apparatus includes an exposure tool, including a photolithography controller; and a computer receiving data from the exposure tool. The computer is programmed to perform a method comprising: identifying a disturbance in a photolithographic process arising from an ambient condition; modeling the identified disturbance; and applying the model to modify a control input parameter.
摘要翻译：本发明在其各个方面是一种用于处理半导体晶片的方法和装置。更具体地，本发明是用于识别和控制环境条件对光刻工艺的影响的方法和装置。在第一方面，本发明是用于处理半导体晶片的方法。该方法包括识别由环境条件引起的光刻工艺中的干扰; 对识别出的干扰进行建模; 并应用该模型来修改控制输入参数。在第二方面，本发明是一种用于控制光刻工艺的设备。所述装置包括曝光工具，包括光刻控制器; 以及从曝光工具接收数据的计算机。计算机被编程为执行一种方法，包括：识别由环境条件引起的光刻过程中的干扰; 对识别出的干扰进行建模; 并应用该模型来修改控制输入参数。

57. 发明授权

US06355388B1 Method for controlling photoresist strip processes 有权
标题翻译：控制光刻胶剥离工艺的方法
公开(公告)号：US06355388B1
公开(公告)日：2002-03-12
申请号：US09414274
申请日：1999-10-07
申请人： Anthony J. Toprac
发明人： Anthony J. Toprac
IPC分类号： G03F900
CPC分类号： G03F7/427 , G03F7/422
摘要： A method for fabricating wafers is provided. A photoresist layer is formed on a wafer. A first thickness of the photoresist layer is measured, and a portion of the photoresist layer is removed. A second thickness of a remainder portion of the photoresist layer is measured. A photoresist strip rate is determined based on the first and second thicknesses, and a recipe of a developer is modified based on the photoresist strip rate. A wafer processing system includes a stepper, a developer, and an automatic process controller. The stepper is adapted to expose a wafer having a photoresist layer deposited thereon. The developer is adapted to remove at least a portion of the photoresist layer based on a recipe. The process controller is adapted to receive a photoresist strip rate and modify the recipe based on the photoresist strip rate.
摘要翻译：提供了一种制造晶片的方法。在晶片上形成光致抗蚀剂层。测量光致抗蚀剂层的第一厚度，并去除光致抗蚀剂层的一部分。测量光致抗蚀剂层的剩余部分的第二厚度。基于第一厚度和第二厚度确定光致抗蚀剂剥离速率，并且基于光致抗蚀剂剥离速率修改显影剂的配方。晶片处理系统包括步进机，显影器和自动过程控制器。步进器适于暴露其上沉积有光致抗蚀剂层的晶片。显影剂适于基于配方去除至少一部分光致抗蚀剂层。过程控制器适于接收光致抗蚀剂剥离率并且基于光致抗蚀剂剥离速率修改配方。

58. 发明授权

US06228663B1 Method of forming semiconductor devices using gate insulator thickness and channel length for controlling drive current strength 失效
标题翻译：使用栅极绝缘体厚度和沟道长度形成半导体器件以控制驱动电流强度的方法
公开(公告)号：US06228663B1
公开(公告)日：2001-05-08
申请号：US08994107
申请日：1997-12-19
申请人： Mark I. Gardner , H. Jim Fulford , Anthony J. Toprac
发明人： Mark I. Gardner , H. Jim Fulford , Anthony J. Toprac
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L21/28035 , H01L21/28167 , H01L21/28194 , H01L22/20 , H01L29/42364 , H01L29/42376 , Y10S148/162 , Y10S438/945
摘要： A semiconductor device having a controlled drive current strength is produced by varying gate electrode length to accommodate any variation in insulating layer thickness from a desired value. After formation of the gate insulating layer on a substrate, the thickness is measured and compared to a desired value. Based on any differences between the measured and desired values, the length of the gate electrode is determined in order to counteract the variation in gate insulating layer thickness. This results in a change in channel length that counteracts the effect of the variation in insulating layer thickness on the drive current strength. The present process permits close control over the drive current strength of semiconductor devices. This also can provide decreased variation within and between lots and corresponding increases in productivity.
摘要翻译：具有受控的驱动电流强度的半导体器件通过改变栅电极长度来产生，以适应绝缘层厚度的任何变化与期望值。在基板上形成栅极绝缘层之后，测量厚度并将其与期望值进行比较。基于测量值和期望值之间的任何差异，确定栅电极的长度以抵消栅极绝缘层厚度的变化。这导致沟道长度的改变，其抵消了绝缘层厚度变化对驱动电流强度的影响。本方法允许密切控制半导体器件的驱动电流强度。这也可以在批次之间和之间提供减小的变化，并且相应地提高生产率。

59. 发明授权

US6136616A Method of forming semiconductor devices using gate electrode dimensions and dopant concentration for controlling drive current strength 失效
标题翻译：使用栅极尺寸和掺杂剂浓度形成半导体器件以控制驱动电流强度的方法
公开(公告)号：US6136616A
公开(公告)日：2000-10-24
申请号：US22129
申请日：1998-02-11
申请人： H. Jim Fulford , Anthony J. Toprac , Randy Blair
发明人： H. Jim Fulford , Anthony J. Toprac , Randy Blair
IPC分类号： H01L21/265 , H01L21/336 , H01L21/66 , G01R31/26
CPC分类号： H01L29/6659 , H01L21/2652 , H01L22/20
摘要： A semiconductor device having a controlled drive current strength is produced by varying dopant concentration to accommodate any variation in channel length, which is affected by variations in gate electrode dimension(s) from a desired value. After formation of the gate electrode on a substrate, its dimension(s) is measured and compared to a desired value. Based on any differences between the measured and desired values, the concentration of dopant implanted into the substrate is determined in order to counteract the variation in gate electrode dimension. This results in a change in dopant concentration that counteracts the effect of the variation in gate electrode dimension on the drive current strength. The present process provides enhanced control over the drive current strength of semiconductor devices and provides decreased variation within and between lots and corresponding increases in productivity.
摘要翻译：具有受控的驱动电流强度的半导体器件通过改变掺杂剂浓度来产生，以适应沟道长度的任何变化，其受到期望值的栅电极尺寸的变化的影响。在基板上形成栅电极之后，测量其尺寸并将其与期望值进行比较。基于测量值和期望值之间的任何差异，确定注入到衬底中的掺杂剂的浓度以抵消栅电极尺寸的变化。这导致掺杂剂浓度的变化，其抵消了栅电极尺寸变化对驱动电流强度的影响。本方法提供对半导体器件的驱动电流强度的增强的控制，并且在批次之间和之间提供降低的变化并且相应地提高生产率。

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