专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6136616A Method of forming semiconductor devices using gate electrode dimensions and dopant concentration for controlling drive current strength 失效
标题翻译：使用栅极尺寸和掺杂剂浓度形成半导体器件以控制驱动电流强度的方法
公开(公告)号：US6136616A
公开(公告)日：2000-10-24
申请号：US22129
申请日：1998-02-11
申请人： H. Jim Fulford , Anthony J. Toprac , Randy Blair
发明人： H. Jim Fulford , Anthony J. Toprac , Randy Blair
IPC分类号： H01L21/265 , H01L21/336 , H01L21/66 , G01R31/26
CPC分类号： H01L29/6659 , H01L21/2652 , H01L22/20
摘要： A semiconductor device having a controlled drive current strength is produced by varying dopant concentration to accommodate any variation in channel length, which is affected by variations in gate electrode dimension(s) from a desired value. After formation of the gate electrode on a substrate, its dimension(s) is measured and compared to a desired value. Based on any differences between the measured and desired values, the concentration of dopant implanted into the substrate is determined in order to counteract the variation in gate electrode dimension. This results in a change in dopant concentration that counteracts the effect of the variation in gate electrode dimension on the drive current strength. The present process provides enhanced control over the drive current strength of semiconductor devices and provides decreased variation within and between lots and corresponding increases in productivity.
摘要翻译：具有受控的驱动电流强度的半导体器件通过改变掺杂剂浓度来产生，以适应沟道长度的任何变化，其受到期望值的栅电极尺寸的变化的影响。在基板上形成栅电极之后，测量其尺寸并将其与期望值进行比较。基于测量值和期望值之间的任何差异，确定注入到衬底中的掺杂剂的浓度以抵消栅电极尺寸的变化。这导致掺杂剂浓度的变化，其抵消了栅电极尺寸变化对驱动电流强度的影响。本方法提供对半导体器件的驱动电流强度的增强的控制，并且在批次之间和之间提供降低的变化并且相应地提高生产率。

2. 发明授权

US06228663B1 Method of forming semiconductor devices using gate insulator thickness and channel length for controlling drive current strength 失效
标题翻译：使用栅极绝缘体厚度和沟道长度形成半导体器件以控制驱动电流强度的方法
公开(公告)号：US06228663B1
公开(公告)日：2001-05-08
申请号：US08994107
申请日：1997-12-19
申请人： Mark I. Gardner , H. Jim Fulford , Anthony J. Toprac
发明人： Mark I. Gardner , H. Jim Fulford , Anthony J. Toprac
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L21/28035 , H01L21/28167 , H01L21/28194 , H01L22/20 , H01L29/42364 , H01L29/42376 , Y10S148/162 , Y10S438/945
摘要： A semiconductor device having a controlled drive current strength is produced by varying gate electrode length to accommodate any variation in insulating layer thickness from a desired value. After formation of the gate insulating layer on a substrate, the thickness is measured and compared to a desired value. Based on any differences between the measured and desired values, the length of the gate electrode is determined in order to counteract the variation in gate insulating layer thickness. This results in a change in channel length that counteracts the effect of the variation in insulating layer thickness on the drive current strength. The present process permits close control over the drive current strength of semiconductor devices. This also can provide decreased variation within and between lots and corresponding increases in productivity.
摘要翻译：具有受控的驱动电流强度的半导体器件通过改变栅电极长度来产生，以适应绝缘层厚度的任何变化与期望值。在基板上形成栅极绝缘层之后，测量厚度并将其与期望值进行比较。基于测量值和期望值之间的任何差异，确定栅电极的长度以抵消栅极绝缘层厚度的变化。这导致沟道长度的改变，其抵消了绝缘层厚度变化对驱动电流强度的影响。本方法允许密切控制半导体器件的驱动电流强度。这也可以在批次之间和之间提供减小的变化，并且相应地提高生产率。

3. 发明授权

US06271114B1 System for adjusting the size of conductive lines based upon the contact size 失效
标题翻译：基于接触尺寸调整导线尺寸的系统
公开(公告)号：US06271114B1
公开(公告)日：2001-08-07
申请号：US09587809
申请日：2000-06-06
申请人： H. Jim Fulford
发明人： H. Jim Fulford
IPC分类号： H01L214763
CPC分类号： H01L21/76838 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to a method of forming conductive interconnections in an integrated circuit device to optimize or at least maintain the speed at which signals propagate throughout the integrated circuit device. In one embodiment, the method comprises determining any variation in the size of a contact, as compared to its design size, and varying the size of a conductive line to be coupled to the contact based upon the variation in the size of the contact.
摘要翻译：本发明涉及一种在集成电路器件中形成导电互连的方法，以优化或至少保持信号在整个集成电路器件中传播的速度。在一个实施例中，该方法包括与其设计尺寸相比确定接触件的尺寸的任何变化，以及基于接触件尺寸的变化来改变要耦合到接触件的导线的尺寸。

4. 发明授权

US06261909B1 Semiconductor device having ultra shallow junctions and a reduced channel length and method for making same 有权
标题翻译：具有超浅结的半导体器件和减小的沟道长度及其制造方法
公开(公告)号：US06261909B1
公开(公告)日：2001-07-17
申请号：US09225389
申请日：1999-01-05
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L29/66613 , H01L29/7834
摘要： The present invention is directed to a method of forming a transistor having very shallow junctions and a reduced channel length, and a transistor incorporating same. In general, the method comprises forming a first process layer above a semiconducting substrate, and forming a second process layer comprised of an oxidation resistant material above the first process layer. The method continues with the formation of an opening in the first and second process layers and oxidation of the substrate lying within the opening to form a third process layer. Next, a second opening is formed in the third process layer, and a plurality of sidewall spacers are formed in the second opening. The method concludes with the formation of a gate dielectric above the substrate and between the sidewall spacers, the formation of a gate conductor above the gate dielectric, and the formation of a plurality of source and drain regions in the substrate. The transistor is comprised of a recess formed in the substrate, a gate dielectric positioned above the substrate lying within the recess, the interface between said gate dielectric and said substrate being positioned beneath the surface of said substrate. The transistor further comprises a gate conductor positioned above the gate dielectric, a plurality of sidewall spacers positioned adjacent the gate conductor, and a plurality of source/drain regions formed in the substrate.
摘要翻译：本发明涉及一种形成具有非常浅的结和减小的沟道长度的晶体管的方法，以及并入其的晶体管。通常，该方法包括在半导体衬底上形成第一工艺层，以及形成由第一工艺层上方的耐氧化材料构成的第二工艺层。该方法继续在第一和第二处理层中形成开口并且位于开口内的基板的氧化以形成第三处理层。接下来，在第三处理层中形成第二开口，并且在第二开口中形成多个侧壁间隔物。该方法的结论是在衬底之上和侧壁间隔物之间形成栅极电介质，在栅极电介质上形成栅极导体，以及在衬底中形成多个源极和漏极区域。晶体管由形成在基板中的凹槽，位于凹槽内的基板上方的栅介质构成，所述栅极电介质和所述基板之间的界面位于所述基板的表面之下。晶体管还包括位于栅极电介质上方的栅极导体，邻近栅极导体定位的多个侧壁间隔件，以及形成在基板中的多个源极/漏极区域。

5. 发明授权

US06245638B1 Trench and gate dielectric formation for semiconductor devices 有权
标题翻译：用于半导体器件的沟槽和栅极电介质形成
公开(公告)号：US06245638B1
公开(公告)日：2001-06-12
申请号：US09128235
申请日：1998-08-03
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/823462 , H01L21/823481 , Y10S148/05
摘要： Semiconductor device fabrication techniques which integrate the formation of trench isolation areas and gate insulating layers are provided. The fabrication techniques include forming one or more sacrificial layers, such as nitrided oxide layers, over regions of the substrate adjacent to a trench isolation region. The sacrificial layers are then removed prior to gate insulating layer formation. The formation of the sacrificial layers improves the trench structure and also improves the substrate surface for the subsequent formation of the gate insulating layer and gate electrode.
摘要翻译：提供集成沟槽隔离区域和栅极绝缘层的形成的半导体器件制造技术。制造技术包括在与沟槽隔离区相邻的衬底的区域上形成一个或多个牺牲层，例如氮化氧化物层。然后在形成栅极绝缘层之前去除牺牲层。牺牲层的形成改善了沟槽结构，并且还改善了衬底表面，以便随后形成栅极绝缘层和栅电极。

6. 发明授权

US06207995B1 High K integration of gate dielectric with integrated spacer formation for high speed CMOS 有权
标题翻译：高K集成栅极电介质与高速CMOS的集成间隔物形成
公开(公告)号：US06207995B1
公开(公告)日：2001-03-27
申请号：US09255917
申请日：1999-02-23
申请人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford
发明人： Mark I. Gardner , Dim-Lee Kwong , H. Jim Fulford
IPC分类号： H01L2976
CPC分类号： H01L21/28194 , H01L29/42368 , H01L29/516 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/66598 , H01L29/78391
摘要： An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the method includes the steps of forming a gate insulating layer on the substrate with a first outwardly tapered sidewall and a second outwardly tapered sidewall. A gate electrode is formed on the gate insulating layer. A first source/drain region and a second source/drain region are formed in the substrate by implanting ions into the substrate, wherein a first portion of the ions passes through the first sidewall and a second portion of the ions passes through the second sidewall. The method provides for incorporation of spacer-like structure into a gate dielectric layer. Conventional spacer fabrication may be eliminated and graded source/drain regions established with a single implant.
摘要翻译：提供集成电路及其制造晶体管的方法。在一个方面，该方法包括以下步骤：在衬底上形成具有第一向外锥形侧壁和第二向外渐缩侧壁的栅极绝缘层。在栅极绝缘层上形成栅电极。通过将离子注入衬底而在衬底中形成第一源/漏区和第二源极/漏极区，其中离子的第一部分穿过第一侧壁，并且离子的第二部分通过第二侧壁。该方法提供了将间隔物结构结合到栅介质层中。可以消除传统的间隔物制造，并用单个植入物建立分级的源极/漏极区域。

7. 发明授权

US06204148B1 Method of making a semiconductor device having a grown polysilicon layer 有权
标题翻译：制造具有生长的多晶硅层的半导体器件的方法
公开(公告)号：US06204148B1
公开(公告)日：2001-03-20
申请号：US09329843
申请日：1999-06-11
申请人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford , Derick J. Wristers
IPC分类号： H01L2176
CPC分类号： H01L29/66583
摘要： A partially formed semiconductor device includes a substrate, a first layer, a layer of polysilicon, and a grown layer of polysilicon. The first layer is positioned above at least a portion of the substrate. The layer of polysilicon is positioned above at least a portion of the first layer and has a first opening formed therein. The first opening has a first width that is defined by a plurality of sidewalls. The grown layer of polysilicon is positioned adjacent at least the plurality of sidewalls and the grown layer of polysilicon defines a second opening. The second opening has a second width with the second width being less than the first width. A method for partially forming a semiconductor device includes forming a process layer above at least a portion of a substrate. A layer of polysilicon is formed above at least a portion of the process layer. An opening is formed in the layer of polysilicon, and the opening has a first width that is defined by a plurality of sidewalls. The first width of the opening is reduced to a second width by growing a layer of polysilicon adjacent at least a portion of the sidewalls of the opening.
摘要翻译：部分形成的半导体器件包括衬底，第一层，多晶硅层和生长的多晶硅层。第一层位于衬底的至少一部分上方。多晶硅层位于第一层的至少一部分的上方，并且其中形成有第一开口。第一开口具有由多个侧壁限定的第一宽度。多晶硅生长层位于至少多个侧壁附近，并且生长的多晶硅层限定第二开口。第二开口具有第二宽度，第二宽度小于第一宽度。部分形成半导体器件的方法包括在衬底的至少一部分上方形成工艺层。在工艺层的至少一部分上方形成多晶硅层。在多晶硅层中形成开口，并且开口具有由多个侧壁限定的第一宽度。通过在开口的侧壁的至少一部分附近生长一层多晶硅，将开口的第一宽度减小到第二宽度。

8. 发明授权

US6107150A Method of making high performance transistors using channel modulated implant for ultra thin oxide formation 有权
标题翻译：使用通道调制植入物制造高性能晶体管的方法，用于超薄氧化物形成
公开(公告)号：US6107150A
公开(公告)日：2000-08-22
申请号：US148095
申请日：1998-09-04
申请人： Mark I. Gardner , H. Jim Fulford
发明人： Mark I. Gardner , H. Jim Fulford
IPC分类号： H01L21/265 , H01L21/28 , H01L29/51 , H01L21/336
CPC分类号： H01L21/28185 , H01L21/26506 , H01L21/28176 , H01L21/28202 , H01L21/2822 , H01L29/518 , Y10T408/89 , Y10T408/9065
摘要： The present invention is directed to a semiconductor device having an ultra thin gate oxide and a method for making same. The method is comprised of implanting nitrogen into a region of a semiconducting substrate, and forming a gate dielectric above the region in the substrate. The method further comprises forming a gate conductor above the gate dielectric and forming at least one source/drain region. The present invention is also directed to a transistor having a gate dielectric positioned above a surface of a semiconducting substrate, the gate dielectric being comprised of a nitrogen bearing oxide having a nitrogen concentration ranging from approximately 4-8%. The transistor further comprises a gate conductor positioned above the gate dielectric and at least one source/drain region.
摘要翻译：本发明涉及一种具有超薄栅极氧化物的半导体器件及其制造方法。该方法包括将氮注入到半导体衬底的区域中，以及在衬底中的区域的上方形成栅极电介质。该方法还包括在栅极电介质上方形成栅极导体，并形成至少一个源极/漏极区域。本发明还涉及一种晶体管，其具有位于半导体衬底的表面上方的栅极电介质，该栅极电介质由具有约4-8％的氮浓度的含氮氧化物构成。晶体管还包括位于栅极介质上方的栅极导体和至少一个源极/漏极区域。

9. 发明授权

US6090676A Process for making high performance MOSFET with scaled gate electrode thickness 失效
标题翻译：制造具有缩放栅电极厚度的高性能MOSFET的工艺
公开(公告)号：US6090676A
公开(公告)日：2000-07-18
申请号：US149210
申请日：1998-09-08
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/423
CPC分类号： H01L29/66583 , H01L21/2652 , H01L21/28114 , H01L29/42376 , H01L29/66598
摘要： A process for making a high performance MOSFET with a scaled gate electrode thickness. In one embodiment, the process comprises first providing a substrate. A gate dielectric layer is formed on the substrate, and a gate electrode is formed on the gate dielectric layer. A middle portion of the gate electrode has a first height, and side portions of the gate electrode have heights that are less than the first height. A dopant species is implanted at a first energy level and at a first concentration, whereby lightly doped drain regions are formed in the substrate below the side portions of the gate electrode.
摘要翻译：制造具有定标栅极电极厚度的高性能MOSFET的工艺。在一个实施例中，该方法包括首先提供衬底。在基板上形成栅介电层，在栅介质层上形成栅电极。栅电极的中间部分具有第一高度，并且栅电极的侧部具有小于第一高度的高度。以第一能级和第一浓度注入掺杂剂物质，由此在栅电极的侧部下方的衬底中形成轻掺杂漏极区。

10. 发明授权

US5977602A Semiconductor device having an oxygen-rich punchthrough region extending through the length of the active region 失效
标题翻译：具有延伸穿过有源区的长度的富氧穿透区域的半导体器件
公开(公告)号：US5977602A
公开(公告)日：1999-11-02
申请号：US995076
申请日：1997-12-19
申请人： Mark I. Gardner , H. Jim Fulford
发明人： Mark I. Gardner , H. Jim Fulford
IPC分类号： H01L21/265 , H01L21/336 , H01L21/762 , H01L29/06 , H01L29/10 , H01L29/54
CPC分类号： H01L21/76243 , H01L29/0649 , H01L29/0653 , H01L29/1079 , H01L29/6659 , H01L29/66772 , H01L21/26506 , H01L21/26533
摘要： A semiconductor device having an oxygen-rich punchthrough region under the channel region, and a process for fabricating such a device are disclosed. In accordance with one embodiment, a semiconductor device is formed by forming an oxygen-rich punchthrough region in a substrate, and forming a channel region over the oxygen-rich punchthrough region. The use of an oxygen-rich punchthrough region may, for example, inhibit the diffusion of dopants used in forming the channel region.
摘要翻译：公开了一种在通道区域下方具有富氧穿透区域的半导体器件及其制造方法。根据一个实施例，通过在衬底中形成富氧穿透区域并在富氧穿透区域上形成沟道区域形成半导体器件。例如，使用富氧穿透区域可以抑制在形成沟道区域中使用的掺杂剂的扩散。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式