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51. 发明授权

US08907441B2 Methods for double-patterning-compliant standard cell design 有权
标题翻译：符合双重图案的标准电池设计方法
公开(公告)号：US08907441B2
公开(公告)日：2014-12-09
申请号：US12702885
申请日：2010-02-09
申请人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
IPC分类号： H01L21/70 , H01L27/02 , H01L23/528 , H01L27/118
CPC分类号： G06F17/5072 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
摘要翻译：半导体芯片包括一行单元，其中每个单元包括VDD线和VSS线。单元的所有VDD线连接为单个VDD线，并且单元的所有VSS线都以单个VSS线连接。在单元格行中不存在具有偶数个G0路径的双重图案化完整轨迹，或者在单元行中不存在具有奇数个G0路径的双图案化完整轨迹。

52. 发明授权

US08775977B2 Decomposition and marking of semiconductor device design layout in double patterning lithography 有权
标题翻译：半双工图案平版印刷中半导体器件设计布局的分解和标记
公开(公告)号：US08775977B2
公开(公告)日：2014-07-08
申请号：US13027520
申请日：2011-02-15
申请人： Chin-Chang Hsu , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
发明人： Chin-Chang Hsu , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F7/70433 , G03F7/70466
摘要： Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.
摘要翻译：提供了一种用于评估半导体器件级的设计布局并通过分解设计布局来确定和指定由不同光掩模形成的设计布局的不同特征的系统和方法。这些特征由标记指定，该标记将各种器件特征与将在其上形成的多个光掩模相关联，然后使用双重图案化光刻DPL技术在半导体器件层面上产生。标记是在设备级完成的，并被包括在由设计公司提供给光掩模铸造厂的电子文件中。除了正在分解的设计布局的重叠和关键维度考虑之外，在确定和标记各种设备时，还考虑了各种其他设备标准，设计标准处理标准及其相关性以及设备环境和其他设备层特征。

53. 发明授权

US08434032B2 Method of generating an intellectual property block design kit, method of generating an integrated circuit design, and simulation system for the integrated circuit design 有权
标题翻译：生成知识产权块设计套件的方法，集成电路设计的生成方法和集成电路设计的仿真系统
公开(公告)号：US08434032B2
公开(公告)日：2013-04-30
申请号：US12950371
申请日：2010-11-19
申请人： Lee-Chung Lu , Yun-Han Lee , Wei-Li Chen , Tan-Li Chou , Kheng-Guan Tan , Shi-Hung Wang
发明人： Lee-Chung Lu , Yun-Han Lee , Wei-Li Chen , Tan-Li Chou , Kheng-Guan Tan , Shi-Hung Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F2217/02 , G06F2217/66
摘要： The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for manufacturing an integrated circuit. According at least one embodiment, the IP block circuit design is generated. The IP block circuit design is simulated based on predetermined configuration sets, and each configuration set has manufacturing options and/or operating conditions. A plurality of system-level models for the predetermined configuration sets are generated based on the simulation of the IP block circuit design. The system-level characteristics table is generated by arranging the predetermined configuration sets and the system-level models in compliance with a system-level characteristics table template of a system-level characteristics modeling device. Then the IP block circuit design and the system-level characteristics table are stored as the IP block design kit.
摘要翻译：本申请公开了一种生成包括IP块电路设计和用于制造集成电路的系统级特性表的知识产权（IP）块设计套件的方法。根据至少一个实施例，产生IP块电路设计。 IP块电路设计基于预定的配置集进行仿真，每个配置集都具有制造选项和/或操作条件。基于IP块电路设计的仿真，生成用于预定配置集的多个系统级模型。通过根据系统级特征建模设备的系统级特征表模板布置预定配置集和系统级模型来生成系统级特征表。然后将IP块电路设计和系统级特性表存储为IP块设计工具包。

54. 发明授权

US08431985B2 Layout and process of forming contact plugs 有权
标题翻译：形成接触塞的布局和工艺
公开(公告)号：US08431985B2
公开(公告)日：2013-04-30
申请号：US12852274
申请日：2010-08-06
申请人： Yung-Chin Hou , Lee-Chung Lu , Shyue-Shyh Lin , Li-Chun Tien
发明人： Yung-Chin Hou , Lee-Chung Lu , Shyue-Shyh Lin , Li-Chun Tien
IPC分类号： H01L29/66
CPC分类号： H01L21/823475 , H01L21/76816 , H01L29/66545
摘要： A device includes a semiconductor substrate including an active region, a gate electrode directly over the active region, and a gate contact plug over and electrically coupled to the gate electrode. The gate contact plug includes at least a portion directly over, and vertically overlapping, the active region.
摘要翻译：一种器件包括半导体衬底，该半导体衬底包括有源区，直接在有源区上方的栅电极以及与该栅电极电连接的栅接触插塞。栅极接触插塞包括至少一个直接在有源区域上方并且垂直重叠的部分。

55. 发明授权

US08356262B1 Cell architecture and method 有权
标题翻译：单元架构和方法
公开(公告)号：US08356262B1
公开(公告)日：2013-01-15
申请号：US13207506
申请日：2011-08-11
申请人： Lee-Chung Lu , Li-Chun Tien , Shyue-Shyh Lin , Zhe-Wei Jiang
发明人： Lee-Chung Lu , Li-Chun Tien , Shyue-Shyh Lin , Zhe-Wei Jiang
IPC分类号： G06F17/50 , H01L29/40 , H01L23/48 , H01L23/52 , H01L21/44
CPC分类号： G03F1/70 , G06F17/504 , G06F17/5072 , H01L2924/0002 , H01L2924/00
摘要： A method includes selecting a cell stored in a non-transient computer readable storage medium, arranging a plurality of the cells on a model of a semiconductor device, and creating a mask for the semiconductor device based on the model of the semiconductor device. The cell is designed according to a design rule in which a first power-supply-connection via satisfies a criterion from the group consisting of: i) the first power-supply-connection via is spaced apart from a second power-supply-connection via by a distance that is greater than a threshold distance such that the cell can be fabricated by a single-photolithography single-etch process, or ii) the first power-supply-connection via is coupled to first and second substantially parallel conductive lines that extend along directly adjacent tracks.
摘要翻译：一种方法包括：选择存储在非瞬态计算机可读存储介质中的单元，将多个单元布置在半导体器件的模型上，以及基于半导体器件的模型为半导体器件创建掩模。电池根据设计规则设计，其中第一电源连接通孔满足以下组的标准：i）第一电源连接通孔与第二电源连接通路间隔开距离大于阈值距离，使得可以通过单光刻单蚀刻工艺制造单元，或者ii）第一电源连接通孔耦合到第一和第二基本平行的导线，其延伸沿着直接相邻的轨道。

56. 发明授权

US08119310B1 Mask-shift-aware RC extraction for double patterning design 有权
标题翻译：面罩移位感知RC提取双图案设计
公开(公告)号：US08119310B1
公开(公告)日：2012-02-21
申请号：US12872938
申请日：2010-08-31
申请人： Lee-Chung Lu , Yi-Kan Cheng , Hsiao-Shu Chao , Ke-Ying Su , Cheng-Hung Yeh , Dian-Hau Chen , Ru-Gun Liu , Wen-Chun Huang
发明人： Lee-Chung Lu , Yi-Kan Cheng , Hsiao-Shu Chao , Ke-Ying Su , Cheng-Hung Yeh , Dian-Hau Chen , Ru-Gun Liu , Wen-Chun Huang
IPC分类号： G03F9/00 , G06F17/50
CPC分类号： G03F1/70
摘要： A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.
摘要翻译：一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模。确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。

57. 发明授权

US08117575B2 System and method for on-chip-variation analysis 有权
标题翻译：片上变异分析系统和方法
公开(公告)号：US08117575B2
公开(公告)日：2012-02-14
申请号：US12538507
申请日：2009-08-10
申请人： Lee-Chung Lu , Chung-Hsing Wang , Yuan-Te Hou
发明人： Lee-Chung Lu , Chung-Hsing Wang , Yuan-Te Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Apparatus is provided for performing timing analysis on a circuit. A first storage device portion stores a state dependent stage weight for each of a rising time arc and a falling time arc of each of a plurality of cells in a cell library. An adder is provided for calculating a sum of the state dependent stage weights for each of the cells that are included in a circuit path. A second storage device portion stores a table containing on chip variation (OCV) derating factors. The table is indexed by values of the sum. A total path delay is calculated for the circuit path, based on the OCV derating factor corresponding to the sum of the state dependent stage weights for the cells in the circuit path.
摘要翻译：提供了一种用于在电路上执行定时分析的装置。第一存储设备部分存储单元库中的多个单元中的每一个的上升时间弧和下降时间弧中的每一个的状态依赖级加权。提供一个加法器，用于计算包括在电路路径中的每个单元格的状态依赖级加权之和。第二存储设备部分存储包含片上变化（OCV）降额因子的表。该表由值的值索引。基于对应于电路路径中的单元的状态依赖级加权之和的OCV降额因子，计算电路路径的总路径延迟。

58. 发明授权

US07958465B2 Dummy pattern design for reducing device performance drift 有权
标题翻译：用于减少设备性能漂移的虚拟模式设计
公开(公告)号：US07958465B2
公开(公告)日：2011-06-07
申请号：US12211503
申请日：2008-09-16
申请人： Lee-Chung Lu , Chien-Chih Kuo , Jian-Yi Li , Sheng-Jier Yang
发明人： Lee-Chung Lu , Chien-Chih Kuo , Jian-Yi Li , Sheng-Jier Yang
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： H01L27/0207 , G06F2217/12 , Y02P90/265
摘要： A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip.
摘要翻译：在芯片上形成集成电路结构的方法包括：提取包括扩散区域的有源图案; 扩大有源图案以形成具有彼此垂直的第一边缘和第二边缘的虚拟禁止区域; 并且在整个芯片上增加应力阻挡虚拟扩散区域，其包括在虚拟禁止区域的第一边缘附近并基本平行地添加第一应力阻挡虚拟扩散区域; 以及添加与所述伪禁区的所述第二边缘相邻并且基本上平行的第二应力阻挡虚设扩散区。该方法还包括：在整个芯片上添加应力阻挡虚拟扩散区域的步骤之后，将一般的虚拟扩散区域添加到芯片的剩余间隔中。

59. 发明申请

US20110119648A1 ROUTING SYSTEM AND METHOD FOR DOUBLE PATTERNING TECHNOLOGY 有权
标题翻译：双文件技术的路由系统和方法
公开(公告)号：US20110119648A1
公开(公告)日：2011-05-19
申请号：US12649979
申请日：2009-12-30
申请人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.
摘要翻译：一种方法包括接收要包括在IC布局中的多个电路部件的标识。生成表示连接两个电路部件的第一图案的数据。第一图案具有多个片段。至少两个片段具有彼此垂直的纵向方向。保留与至少两个段中的至少一个相邻的至少一个无图案区域。生成表示在第一图案附近的一个或多个附加图案的数据。在无模式区域中没有形成附加图案。第一种图案和附加图案形成双重图案化顺应的图案集合。将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。

60. 发明授权

US07932566B2 Structure and system of mixing poly pitch cell design under default poly pitch design rules 有权
标题翻译：在默认聚沥青设计规则下混合聚沥青单元设计的结构和系统
公开(公告)号：US07932566B2
公开(公告)日：2011-04-26
申请号：US12347628
申请日：2008-12-31
申请人： Yung-Chin Hou , Li-Chun Tien , Lee-Chung Lu , Ping Chung Li , Ta-Pen Guo
发明人： Yung-Chin Hou , Li-Chun Tien , Lee-Chung Lu , Ping Chung Li , Ta-Pen Guo
IPC分类号： H01L25/00
CPC分类号： G06F17/5072 , H01L27/0207 , H01L27/11803
摘要： An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly pitch. A first boundary region has at least one isolation area that lies between the type-1 cells and the type-2 cell in the X-direction. The first boundary region includes at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the default poly pitch of the type-1 cells and a second portion that complies with the non-default poly pitch of the type-2 cell.
摘要翻译：提出了包括1型电池和2型电池的集成电路。 1型电池具有默认聚间距的多线。 2型电池具有具有非默认聚间距的多线。第一边界区域具有位于X方向上的类型1单元和类型2单元之间的至少一个隔离区域。第一边界区域包括至少一个合并的虚拟多线，其中所述至少一个合并虚拟多线具有符合类型-1单元的默认多音调的第一部分和符合非默认的第二部分 2型细胞的聚间距。

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