专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08907441B2 Methods for double-patterning-compliant standard cell design 有权
标题翻译：符合双重图案的标准电池设计方法
公开(公告)号：US08907441B2
公开(公告)日：2014-12-09
申请号：US12702885
申请日：2010-02-09
申请人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
IPC分类号： H01L21/70 , H01L27/02 , H01L23/528 , H01L27/118
CPC分类号： G06F17/5072 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
摘要翻译：半导体芯片包括一行单元，其中每个单元包括VDD线和VSS线。单元的所有VDD线连接为单个VDD线，并且单元的所有VSS线都以单个VSS线连接。在单元格行中不存在具有偶数个G0路径的双重图案化完整轨迹，或者在单元行中不存在具有奇数个G0路径的双图案化完整轨迹。

2. 发明申请

US20110193234A1 Methods for Double-Patterning-Compliant Standard Cell Design 有权
标题翻译：双图案化标准单元设计方法
公开(公告)号：US20110193234A1
公开(公告)日：2011-08-11
申请号：US12702885
申请日：2010-02-09
申请人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
IPC分类号： H01L23/52 , G06F17/50
CPC分类号： G06F17/5072 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
摘要翻译：半导体芯片包括一行单元，其中每个单元包括VDD线和VSS线。单元的所有VDD线连接为单个VDD线，并且单元的所有VSS线都以单个VSS线连接。在单元格行中不存在具有偶数个G0路径的双重图案化完整轨迹，或者在单元行中不存在具有奇数个G0路径的双图案化完整轨迹。

3. 发明申请

US20110119648A1 ROUTING SYSTEM AND METHOD FOR DOUBLE PATTERNING TECHNOLOGY 有权
标题翻译：双文件技术的路由系统和方法
公开(公告)号：US20110119648A1
公开(公告)日：2011-05-19
申请号：US12649979
申请日：2009-12-30
申请人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.
摘要翻译：一种方法包括接收要包括在IC布局中的多个电路部件的标识。生成表示连接两个电路部件的第一图案的数据。第一图案具有多个片段。至少两个片段具有彼此垂直的纵向方向。保留与至少两个段中的至少一个相邻的至少一个无图案区域。生成表示在第一图案附近的一个或多个附加图案的数据。在无模式区域中没有形成附加图案。第一种图案和附加图案形成双重图案化顺应的图案集合。将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。

4. 发明授权

US08239806B2 Routing system and method for double patterning technology 有权
标题翻译：双重图案化技术的路由系统和方法
公开(公告)号：US08239806B2
公开(公告)日：2012-08-07
申请号：US12649979
申请日：2009-12-30
申请人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.
摘要翻译：一种方法包括接收要包括在IC布局中的多个电路部件的标识。生成表示连接两个电路部件的第一图案的数据。第一图案具有多个片段。至少两个片段具有彼此垂直的纵向方向。保留与至少两个段中的至少一个相邻的至少一个无图案区域。生成表示在第一图案附近的一个或多个附加图案的数据。在无模式区域中没有形成附加图案。第一种图案和附加图案形成双重图案化顺应的图案集合。将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。

5. 发明申请

US20100281446A1 Integrated Circuit Design using DFM-Enhanced Architecture 有权
标题翻译：使用DFM增强架构的集成电路设计
公开(公告)号：US20100281446A1
公开(公告)日：2010-11-04
申请号：US12708242
申请日：2010-02-18
申请人： Yung-Chin Hou , Lee-Chung Lu , Li-Chun Tien , Yi-Kan Cheng , Chun-Hui Tai , Ta-Pen Guo , Yuan-Te Hou
发明人： Yung-Chin Hou , Lee-Chung Lu , Li-Chun Tien , Yi-Kan Cheng , Chun-Hui Tai , Ta-Pen Guo , Yuan-Te Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.
摘要翻译：集成电路库包括具有第一左边界和第一右边界的第一标准单元，以及具有第二左边界和第二右边界的第二标准单元。第一标准细胞和第二标准细胞具有相同的细胞变体。第一标准单元中的第一有源区具有与第二标准单元中的第二有源区不同的扩散长度。第一有源区和第二有源区是由表示第一标准单元和第二标准单元的相同电路图的相同分量表示的相应有源区。

6. 发明申请

US20100196803A1 Methods for Cell Boundary Isolation in Double Patterning Design 有权
标题翻译：双重图案设计中细胞边界隔离的方法
公开(公告)号：US20100196803A1
公开(公告)日：2010-08-05
申请号：US12616970
申请日：2009-11-12
申请人： Lee-Chung Lu , Yi-Kan Cheng , Yuan-Te Hou , Yung-Chin Hou , Li-Chun Tien
发明人： Lee-Chung Lu , Yi-Kan Cheng , Yuan-Te Hou , Yung-Chin Hou , Li-Chun Tien
IPC分类号： G03F1/00 , G06F17/50
CPC分类号： G03F1/70 , G03F1/00
摘要： A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.
摘要翻译：设计用于芯片布局的双重图案掩模组的方法包括设计标准单元。在每个标准单元中，所有左边界图案被分配有第一指示符和第二指示符中的一个，并且所有右边图案都被分配有第一指示符和第二指示符中的另外一个。该方法还包括将标准单元放置在芯片布局的一行中。从行中的一个标准单元开始，标记单元的指示符更改在整行中传播。具有第一指示符的标准单元中的所有图案被转移到双图案掩模组的第一掩模。具有第二指示器的标准单元中的所有图案被转移到双重图案掩模组的第二掩模。

7. 发明授权

US08631366B2 Integrated circuit design using DFM-enhanced architecture 有权
标题翻译：采用DFM增强架构的集成电路设计
公开(公告)号：US08631366B2
公开(公告)日：2014-01-14
申请号：US12708242
申请日：2010-02-18
申请人： Yung-Chin Hou , Lee-Chung Lu , Li-Chun Tien , Yi-Kan Cheng , Chun-Hui Tai , Ta-Pen Guo , Yuan-Te Hou
发明人： Yung-Chin Hou , Lee-Chung Lu , Li-Chun Tien , Yi-Kan Cheng , Chun-Hui Tai , Ta-Pen Guo , Yuan-Te Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.
摘要翻译：集成电路库包括具有第一左边界和第一右边界的第一标准单元，以及具有第二左边界和第二右边界的第二标准单元。第一标准细胞和第二标准细胞具有相同的细胞变体。第一标准单元中的第一有源区具有与第二标准单元中的第二有源区不同的扩散长度。第一有源区和第二有源区是由表示第一标准单元和第二标准单元的相同电路图的相同分量表示的相应有源区。

8. 发明授权

US08255837B2 Methods for cell boundary isolation in double patterning design 有权
标题翻译：双图案设计中单元边界隔离的方法
公开(公告)号：US08255837B2
公开(公告)日：2012-08-28
申请号：US12616970
申请日：2009-11-12
申请人： Lee-Chung Lu , Yi-Kan Cheng , Yuan-Te Hou , Yung-Chin Hou , Li-Chun Tien
发明人： Lee-Chung Lu , Yi-Kan Cheng , Yuan-Te Hou , Yung-Chin Hou , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F1/00
摘要： A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.
摘要翻译：设计用于芯片布局的双重图案掩模组的方法包括设计标准单元。在每个标准单元中，所有左边界图案被分配有第一指示符和第二指示符中的一个，并且所有右边图案都被分配有第一指示符和第二指示符中的另外一个。该方法还包括将标准单元放置在芯片布局的一行中。从行中的一个标准单元开始，标记单元的指示符更改在整行中传播。具有第一指示符的标准单元中的所有图案被转移到双图案掩模组的第一掩模。具有第二指示器的标准单元中的所有图案被转移到双重图案掩模组的第二掩模。

9. 发明授权

US08448100B1 Tool and method for eliminating multi-patterning conflicts 有权
标题翻译：消除多图案化冲突的工具和方法
公开(公告)号：US08448100B1
公开(公告)日：2013-05-21
申请号：US13444158
申请日：2012-04-11
申请人： Hung Lung Lin , Chin-Chang Hsu , Ying-Yu Shen , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng , Chin-Hsiung Hsu , Huang-Yu Chen , Yi-Chuin Tsai , Yuan-Te Hou , Chung-Hsing Wang
发明人： Hung Lung Lin , Chin-Chang Hsu , Ying-Yu Shen , Wen-Ju Yang , Hsiao-Shu Chao , Yi-Kan Cheng , Chin-Hsiung Hsu , Huang-Yu Chen , Yi-Chuin Tsai , Yuan-Te Hou , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A computer implemented system comprises: a tangible, non-transitory computer readable storage medium encoded with data representing an initial layout of an integrated circuit pattern layer having a plurality of polygons. A special-purpose computer is configured to perform the steps of: analyzing in the initial layout of an integrated circuit pattern layer having a plurality of polygons, so as to identify a plurality of multi-patterning conflict cycles in the initial layout; constructing in the computer a respective multi-patterning conflict cycle graph representing each identified multi-patterning conflict cycle; classifying each identified multi-patterning conflict cycle graph in the computer according to a number of other multi-patterning conflict cycle graphs which enclose that multi-patterning conflict cycle graph; and causing a display device to graphically display the plurality of multi-patterning conflict cycle graphs according to their respective classifications.
摘要翻译：计算机实现的系统包括：编码有表示具有多个多边形的集成电路图案层的初始布局的数据的有形的，非暂时性的计算机可读存储介质。专用计算机被配置为执行以下步骤：在具有多个多边形的集成电路图案层的初始布局中进行分析，以便在初始布局中识别多个多图案化冲突循环; 在计算机中构建表示每个识别的多图案化冲突周期的相应的多图案化冲突循环图; 根据围绕该多图案化冲突循环图的其他多图案化冲突循环图的数量，在计算机中分类每个识别的多图案化冲突循环图; 并且使得显示装置根据它们各自的分类图形地显示多个多图案化冲突循环图。

10. 发明申请

US20120131528A1 METHOD AND APPARATUS FOR ACHIEVING MULTIPLE PATTERNING TECHNOLOGY COMPLIANT DESIGN LAYOUT 有权
标题翻译：实现多种图案技术的方法和装置合规设计布局
公开(公告)号：US20120131528A1
公开(公告)日：2012-05-24
申请号：US12953661
申请日：2010-11-24
申请人： Huang-Yu Chen , Fang-Yu Fan , Yuan-Te Hou , Lee-Chung Lu , Ru-Gun Liu , Ken-Hsien Hsieh , Lee Fung Song , Wen-Chun Huang , Li-Chun Tien
发明人： Huang-Yu Chen , Fang-Yu Fan , Yuan-Te Hou , Lee-Chung Lu , Ru-Gun Liu , Ken-Hsien Hsieh , Lee Fung Song , Wen-Chun Huang , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G03F7/70433 , G03F7/70466
摘要： A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color.
摘要翻译：提供了一种用于实现多个图案化兼容技术设计布局的方法和装置。示例性方法包括提供具有路由轨迹的路由网格; 指定每个路线轨道至少两种颜色之一; 将具有多个特征的图案布局应用于所述路由网格，其中所述多个特征中的每一个对应于至少一个路由轨道; 以及应用特征分解约束来确定所述图案布局是否是符合多重图案化的布局。如果图案布局不是符合多重图案化的布局，则可以修改图案布局，直到实现多重图案化兼容布局。如果图案布局是符合多重图案化的布局，则该方法包括基于每个特征对应的至少一个路线轨迹的颜色来着色多个特征中的每一个，从而形成彩色图案布局，并且生成至少两个具有彩色图案布局的特点。每个面具都包含单一颜色的特征。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式