专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08356262B1 Cell architecture and method 有权
标题翻译：单元架构和方法
公开(公告)号：US08356262B1
公开(公告)日：2013-01-15
申请号：US13207506
申请日：2011-08-11
申请人： Lee-Chung Lu , Li-Chun Tien , Shyue-Shyh Lin , Zhe-Wei Jiang
发明人： Lee-Chung Lu , Li-Chun Tien , Shyue-Shyh Lin , Zhe-Wei Jiang
IPC分类号： G06F17/50 , H01L29/40 , H01L23/48 , H01L23/52 , H01L21/44
CPC分类号： G03F1/70 , G06F17/504 , G06F17/5072 , H01L2924/0002 , H01L2924/00
摘要： A method includes selecting a cell stored in a non-transient computer readable storage medium, arranging a plurality of the cells on a model of a semiconductor device, and creating a mask for the semiconductor device based on the model of the semiconductor device. The cell is designed according to a design rule in which a first power-supply-connection via satisfies a criterion from the group consisting of: i) the first power-supply-connection via is spaced apart from a second power-supply-connection via by a distance that is greater than a threshold distance such that the cell can be fabricated by a single-photolithography single-etch process, or ii) the first power-supply-connection via is coupled to first and second substantially parallel conductive lines that extend along directly adjacent tracks.
摘要翻译：一种方法包括：选择存储在非瞬态计算机可读存储介质中的单元，将多个单元布置在半导体器件的模型上，以及基于半导体器件的模型为半导体器件创建掩模。电池根据设计规则设计，其中第一电源连接通孔满足以下组的标准：i）第一电源连接通孔与第二电源连接通路间隔开距离大于阈值距离，使得可以通过单光刻单蚀刻工艺制造单元，或者ii）第一电源连接通孔耦合到第一和第二基本平行的导线，其延伸沿着直接相邻的轨道。

2. 发明授权

US08239806B2 Routing system and method for double patterning technology 有权
标题翻译：双重图案化技术的路由系统和方法
公开(公告)号：US08239806B2
公开(公告)日：2012-08-07
申请号：US12649979
申请日：2009-12-30
申请人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.
摘要翻译：一种方法包括接收要包括在IC布局中的多个电路部件的标识。生成表示连接两个电路部件的第一图案的数据。第一图案具有多个片段。至少两个片段具有彼此垂直的纵向方向。保留与至少两个段中的至少一个相邻的至少一个无图案区域。生成表示在第一图案附近的一个或多个附加图案的数据。在无模式区域中没有形成附加图案。第一种图案和附加图案形成双重图案化顺应的图案集合。将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。

3. 发明申请

US20110119648A1 ROUTING SYSTEM AND METHOD FOR DOUBLE PATTERNING TECHNOLOGY 有权
标题翻译：双文件技术的路由系统和方法
公开(公告)号：US20110119648A1
公开(公告)日：2011-05-19
申请号：US12649979
申请日：2009-12-30
申请人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.
摘要翻译：一种方法包括接收要包括在IC布局中的多个电路部件的标识。生成表示连接两个电路部件的第一图案的数据。第一图案具有多个片段。至少两个片段具有彼此垂直的纵向方向。保留与至少两个段中的至少一个相邻的至少一个无图案区域。生成表示在第一图案附近的一个或多个附加图案的数据。在无模式区域中没有形成附加图案。第一种图案和附加图案形成双重图案化顺应的图案集合。将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。

4. 发明申请

US20130024832A1 DFM Improvement Utility with Unified Interface 有权
标题翻译：带统一接口的DFM改进实用程序
公开(公告)号：US20130024832A1
公开(公告)日：2013-01-24
申请号：US13186241
申请日：2011-07-19
申请人： Wen-Hao Chen , Zhe-Wei Jiang , Chung-Min Fu
发明人： Wen-Hao Chen , Zhe-Wei Jiang , Chung-Min Fu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.
摘要翻译：一种实用程序包括：被配置为检查集成电路的布局图案的制造设计（DFM）检查器，以及布局改变指令生成器，其被配置为基于由DFM检验器生成的结果生成布局改变指令。 DFM检查器和布局改变指令生成器体现在非暂时性的存储介质上。布局改变指令指定布局图案之间的布局图案的标识符以及要在布局图案上执行的相应布局改变。

5. 发明授权

US08726208B2 DFM improvement utility with unified interface 有权
标题翻译：具有统一接口的DFM改进实用程序
公开(公告)号：US08726208B2
公开(公告)日：2014-05-13
申请号：US13186241
申请日：2011-07-19
申请人： Wen-Hao Chen , Zhe-Wei Jiang , Chung-Min Fu
发明人： Wen-Hao Chen , Zhe-Wei Jiang , Chung-Min Fu
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.
摘要翻译：一种实用程序包括：被配置为检查集成电路的布局图案的制造设计（DFM）检查器，以及布局改变指令生成器，其被配置为基于由DFM检验器生成的结果生成布局改变指令。 DFM检查器和布局改变指令生成器体现在非暂时性的存储介质上。布局改变指令指定布局图案之间的布局图案的标识符以及要在布局图案上执行的各自的布局改变。

6. 发明申请

US20110304010A1 ELECTROSTATIC DISCHARGE PROTECTION SCHEME FOR SEMICONDUCTOR DEVICE STACKING PROCESS 审中-公开
标题翻译：用于半导体器件堆叠工艺的静电放电保护方案
公开(公告)号：US20110304010A1
公开(公告)日：2011-12-15
申请号：US12851539
申请日：2010-08-05
申请人： Zhe-Wei Jiang , Ding-Ming Kwai , Shih-Hung Chen
发明人： Zhe-Wei Jiang , Ding-Ming Kwai , Shih-Hung Chen
IPC分类号： H01L23/60
CPC分类号： H01L25/0657 , H01L23/3677 , H01L23/481 , H01L23/60 , H01L24/05 , H01L24/16 , H01L24/94 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/13025 , H01L2224/16145 , H01L2224/32145 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/01005 , H01L2924/01014 , H01L2924/01046 , H01L2924/14 , H01L2224/05552
摘要： An electrostatic discharge (ESD) protection scheme for a semiconductor device stacking process is provided, in which an equivalent electrical resistance of a specific path is designed to be less than an equivalent electrical resistance of other paths. Accordingly, when a first active layer and a second active layer in the semiconductor device are stacked, by designing suitable ESD protection cells on such a specific path, electrical charges accumulated on the top layer wafer (or die) select such a specific path over the other paths to be released to the grounded bottom layer wafer (or die), so as to achieve an ESD protection effect. In addition, since such a specific path also serves as a heat dissipation path in a three dimensional integrated circuit (3D IC), an overall heat resistance of the 3D IC may be reduced to improve a heat dissipation effect.
摘要翻译：提供了一种用于半导体器件堆叠处理的静电放电（ESD）保护方案，其中特定路径的等效电阻被设计为小于其他路径的等效电阻。因此，当半导体器件中的第一有源层和第二有源层被堆叠时，通过在这样的特定路径上设计合适的ESD保护单元，积聚在顶层晶片（或管芯）上的电荷选择这样的特定路径其他路径被释放到接地的底层晶片（或裸片）上，以达到ESD保护效果。此外，由于这样的特定路径也用作三维集成电路（3D IC）中的散热路径，所以可以降低3D IC的整体耐热性，从而提高散热效果。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式