专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07958465B2 Dummy pattern design for reducing device performance drift 有权
标题翻译：用于减少设备性能漂移的虚拟模式设计
公开(公告)号：US07958465B2
公开(公告)日：2011-06-07
申请号：US12211503
申请日：2008-09-16
申请人： Lee-Chung Lu , Chien-Chih Kuo , Jian-Yi Li , Sheng-Jier Yang
发明人： Lee-Chung Lu , Chien-Chih Kuo , Jian-Yi Li , Sheng-Jier Yang
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： H01L27/0207 , G06F2217/12 , Y02P90/265
摘要： A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip.
摘要翻译：在芯片上形成集成电路结构的方法包括：提取包括扩散区域的有源图案; 扩大有源图案以形成具有彼此垂直的第一边缘和第二边缘的虚拟禁止区域; 并且在整个芯片上增加应力阻挡虚拟扩散区域，其包括在虚拟禁止区域的第一边缘附近并基本平行地添加第一应力阻挡虚拟扩散区域; 以及添加与所述伪禁区的所述第二边缘相邻并且基本上平行的第二应力阻挡虚设扩散区。该方法还包括：在整个芯片上添加应力阻挡虚拟扩散区域的步骤之后，将一般的虚拟扩散区域添加到芯片的剩余间隔中。

2. 发明申请

US20130130456A1 INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US20130130456A1
公开(公告)日：2013-05-23
申请号：US13722142
申请日：2012-12-20
申请人： Chung-Cheng WU , Ali KESHAVARZI , Fung Ka HING , Ta-Pen GUO , Jiann-Tyng TZENG , Yen-Ming CHEN , Shyue-Shyh LIN , Shyh-Wei WANG , Sheng-Jier YANG , Hsiang-Jen TSENG , David B. Scott , Min CAO
发明人： Chung-Cheng WU , Ali KESHAVARZI , Fung Ka HING , Ta-Pen GUO , Jiann-Tyng TZENG , Yen-Ming CHEN , Shyue-Shyh LIN , Shyh-Wei WANG , Sheng-Jier YANG , Hsiang-Jen TSENG , David B. Scott , Min CAO
IPC分类号： H01L29/66
CPC分类号： H01L29/665 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L27/092 , H01L29/7848 , H01L2224/16225
摘要： A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region.
摘要翻译：一种形成集成电路的方法，包括在衬底上形成第一扩散区域和第二扩散区域，其中所述第一扩散区域被配置为用于第一类型晶体管，所述第二扩散区域被配置为用于第二类型晶体管。该方法还包括在第一扩散区域中形成第一源区和漏区。该方法还包括在第二扩散区域中形成第二源区和漏区。该方法还包括形成跨越第一扩散区域和第二扩散区域延伸的栅电极。该方法还包括形成第一金属层，第二金属层和第三金属层。第一金属层与第一源区电耦合。第二金属层与第一和第二漏极区域电耦合。第三金属层与第二源极区域电耦合。

3. 发明申请

US20110204449A1 Dummy Pattern Design for Reducing Device Performance Drift 失效
标题翻译：用于减少设备性能漂移的虚拟模式设计
公开(公告)号：US20110204449A1
公开(公告)日：2011-08-25
申请号：US13099150
申请日：2011-05-02
申请人： Lee-Chung Lu , Chien-Chih Kuo , Jian-Yi Li , Sheng-Jier Yang
发明人： Lee-Chung Lu , Chien-Chih Kuo , Jian-Yi Li , Sheng-Jier Yang
IPC分类号： H01L27/088 , H01L27/08
CPC分类号： B44C1/227 , B44F1/045 , C03C17/38 , C03C17/42 , C03C2218/33 , C09D9/005 , C25D5/48 , C25D7/08
摘要： A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip.
摘要翻译：在芯片上形成集成电路结构的方法包括：提取包括扩散区域的有源图案; 扩大有源图案以形成具有彼此垂直的第一边缘和第二边缘的虚拟禁止区域; 并且在整个芯片上增加应力阻挡虚拟扩散区域，其包括在虚拟禁止区域的第一边缘附近并基本平行地添加第一应力阻挡虚拟扩散区域; 以及添加与所述伪禁区的所述第二边缘相邻并且基本上平行的第二应力阻挡虚设扩散区。该方法还包括：在整个芯片上添加应力阻挡虚拟扩散区域的步骤之后，将一般的虚拟扩散区域添加到芯片的剩余间隔中。

4. 发明授权

US07598130B2 Method for reducing layout-dependent variations in semiconductor devices 有权
标题翻译：减少半导体器件中与布局有关的变化的方法
公开(公告)号：US07598130B2
公开(公告)日：2009-10-06
申请号：US11529091
申请日：2006-09-28
申请人： Chung-Heng Yang , Yi-Ming Sheu , Sheng-Jier Yang
发明人： Chung-Heng Yang , Yi-Ming Sheu , Sheng-Jier Yang
IPC分类号： H01L21/00
CPC分类号： H01L21/823493 , H01L21/2652 , H01L21/823892
摘要： A method for forming an integrated circuit includes providing a semiconductor substrate, forming a re-implantation blocking layer over the semiconductor substrate, forming a mask over the re-implantation blocking layer, patterning the mask to form an opening, wherein a portion of the re-implantation blocking layer is exposed through the opening, performing an implantation to introduce an impurity into a portion of the semiconductor substrate underlying the opening to form a well region, removing the mask, and removing the re-implantation blocking layer.
摘要翻译：一种用于形成集成电路的方法包括提供半导体衬底，在半导体衬底上形成再注入阻挡层，在重新注入阻挡层上形成掩模，图案化掩模以形成开口，其中一部分re 通过开口暴露植入阻挡层，进行注入以将杂质引入到开口下方的半导体衬底的一部分中以形成阱区，去除掩模，以及去除重新注入阻挡层。

5. 发明授权

US07943961B2 Strain bars in stressed layers of MOS devices 有权
标题翻译：应变棒在MOS器件的应力层
公开(公告)号：US07943961B2
公开(公告)日：2011-05-17
申请号：US12048135
申请日：2008-03-13
申请人： Yen-Sen Wang , Chung-Te Lin , Min Cao , Sheng-Jier Yang
发明人： Yen-Sen Wang , Chung-Te Lin , Min Cao , Sheng-Jier Yang
IPC分类号： H01L23/48
CPC分类号： H01L29/78 , H01L21/76802 , H01L21/76829 , H01L29/7843
摘要： A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.
摘要翻译：半导体结构包括有源区; 覆盖有源区的栅极条; 和金属氧化物半导体（MOS）器件。栅极条的一部分形成MOS器件的栅极。有源区的一部分形成MOS器件的源/漏区。半导体结构还包括MOS器件上的应力区域; 以及在应激源区域内部以及有源区域之外的区域外的无应力区域。

6. 发明申请

US20090282374A1 Dummy Pattern Design for Reducing Device Performance Drift 有权
标题翻译：用于减少设备性能漂移的虚拟模式设计
公开(公告)号：US20090282374A1
公开(公告)日：2009-11-12
申请号：US12211503
申请日：2008-09-16
申请人： Lee-Chung Lu , Chien-Chih Kuo , Jian-Yi Li , Sheng-Jier Yang
发明人： Lee-Chung Lu , Chien-Chih Kuo , Jian-Yi Li , Sheng-Jier Yang
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F2217/12 , Y02P90/265
摘要： A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip.
摘要翻译：在芯片上形成集成电路结构的方法包括：提取包括扩散区域的有源图案; 扩大有源图案以形成具有彼此垂直的第一边缘和第二边缘的虚拟禁止区域; 并且在整个芯片上增加应力阻挡虚拟扩散区域，其包括在虚拟禁止区域的第一边缘附近并基本平行地添加第一应力阻挡虚拟扩散区域; 以及添加与所述伪禁区的所述第二边缘相邻并且基本上平行的第二应力阻挡虚设扩散区。该方法还包括：在整个芯片上添加应力阻挡虚拟扩散区域的步骤之后，将一般的虚拟扩散区域添加到芯片的剩余间隔中。

7. 发明申请

US20090230439A1 Strain Bars in Stressed Layers of MOS Devices 有权
标题翻译： MOS器件应力层中的应变条
公开(公告)号：US20090230439A1
公开(公告)日：2009-09-17
申请号：US12048135
申请日：2008-03-13
申请人： Yen-Sen Wang , Chung-Te Lin , Min Cao , Sheng-Jier Yang
发明人： Yen-Sen Wang , Chung-Te Lin , Min Cao , Sheng-Jier Yang
IPC分类号： H01L29/00
CPC分类号： H01L29/78 , H01L21/76802 , H01L21/76829 , H01L29/7843
摘要： A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.
摘要翻译：半导体结构包括有源区; 覆盖有源区的栅极条; 和金属氧化物半导体（MOS）器件。栅极条的一部分形成MOS器件的栅极。有源区的一部分形成MOS器件的源/漏区。半导体结构还包括MOS器件上的应力区域; 以及在应激源区域内部以及有源区域之外的区域外的无应力区域。

8. 发明申请

US20080081382A1 Method for reducing layout-dependent variations in semiconductor devices 有权
标题翻译：减少半导体器件中与布局有关的变化的方法
公开(公告)号：US20080081382A1
公开(公告)日：2008-04-03
申请号：US11529091
申请日：2006-09-28
申请人： Chung-Heng Yang , Yi-Ming Sheu , Sheng-Jier Yang
发明人： Chung-Heng Yang , Yi-Ming Sheu , Sheng-Jier Yang
IPC分类号： H01L21/66
CPC分类号： H01L21/823493 , H01L21/2652 , H01L21/823892
摘要： A method for forming an integrated circuit includes providing a semiconductor substrate, forming a re-implantation blocking layer over the semiconductor substrate, forming a mask over the re-implantation blocking layer, patterning the mask to form an opening, wherein a portion of the re-implantation blocking layer is exposed through the opening, performing an implantation to introduce an impurity into a portion of the semiconductor substrate underlying the opening to form a well region, removing the mask, and removing the re-implantation blocking layer.
摘要翻译：一种用于形成集成电路的方法包括提供半导体衬底，在半导体衬底上形成再注入阻挡层，在重新注入阻挡层上形成掩模，图案化掩模以形成开口，其中一部分re 通过开口暴露植入阻挡层，进行注入以将杂质引入到开口下方的半导体衬底的一部分中以形成阱区，去除掩模，以及去除重新注入阻挡层。

9. 发明授权

US08362573B2 Integrated circuits and manufacturing methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08362573B2
公开(公告)日：2013-01-29
申请号：US12787966
申请日：2010-05-26
申请人： Chung-Cheng Wu , Ali Keshavarzi , Ka Hing Fung , Ta-Pen Guo , Jiann-Tyng Tzeng , Yen-Ming Chen , Shyue-Shyh Lin , Shyh-Wei Wang , Sheng-Jier Yang , Hsiang-Jen Tseng , David B. Scott , Min Cao
发明人： Chung-Cheng Wu , Ali Keshavarzi , Ka Hing Fung , Ta-Pen Guo , Jiann-Tyng Tzeng , Yen-Ming Chen , Shyue-Shyh Lin , Shyh-Wei Wang , Sheng-Jier Yang , Hsiang-Jen Tseng , David B. Scott , Min Cao
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L27/092 , H01L29/7848 , H01L2224/16225
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域间隔开。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属层与第一源区电耦合。第一金属层和第一扩散区域与第一距离重叠。第二金属层与第一漏极区域和第二漏极区域电耦合。第二金属层和第一扩散区域与第二距离重叠。第一距离大于第二距离。

10. 发明授权

US08350330B2 Dummy pattern design for reducing device performance drift 失效
标题翻译：用于减少设备性能漂移的虚拟模式设计
公开(公告)号：US08350330B2
公开(公告)日：2013-01-08
申请号：US13099150
申请日：2011-05-02
申请人： Lee-Chung Lu , Chien-Chih Kuo , Jian-Yi Li , Sheng-Jier Yang
发明人： Lee-Chung Lu , Chien-Chih Kuo , Jian-Yi Li , Sheng-Jier Yang
IPC分类号： H01L29/78
CPC分类号： B44C1/227 , B44F1/045 , C03C17/38 , C03C17/42 , C03C2218/33 , C09D9/005 , C25D5/48 , C25D7/08
摘要： A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. A structure includes a target diffusion region including a first edge with a first length and a second edge with a second edge perpendicular to the first length. A first stress-blocking dummy diffusion region is adjacent to the first edge, with no dummy diffusions regions therebetween. A second stress-blocking dummy diffusion region is adjacent to the second edge, with no dummy diffusion regions therebetween.
摘要翻译：在芯片上形成集成电路结构的方法包括：提取包括扩散区域的有源图案; 扩大有源图案以形成具有彼此垂直的第一边缘和第二边缘的虚拟禁止区域; 并且在整个芯片上增加应力阻挡虚拟扩散区域，其包括在虚拟禁止区域的第一边缘附近并基本平行地添加第一应力阻挡虚拟扩散区域; 以及添加与所述伪禁区的所述第二边缘相邻并且基本上平行的第二应力阻挡虚设扩散区。该方法还包括：在整个芯片上添加应力阻挡虚拟扩散区域的步骤之后，将一般的虚拟扩散区域添加到芯片的剩余间隔中。一种结构包括目标扩散区域，包括具有第一长度的第一边缘和具有垂直于第一长度的第二边缘的第二边缘。第一应力阻挡虚拟扩散区域与第一边缘相邻，其间没有虚拟扩散区域。第二应力阻挡虚拟扩散区域与第二边缘相邻，其间没有虚拟扩散区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式