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1. 发明申请

US20120032268A1 Layout and Process of Forming Contact Plugs 有权
标题翻译：形成接触插头的布局和工艺
公开(公告)号：US20120032268A1
公开(公告)日：2012-02-09
申请号：US12852274
申请日：2010-08-06
申请人： Yung-Chin Hou , Lee-Chung Lu , Shyue-Shyh Lin , Li-Chun Tien
发明人： Yung-Chin Hou , Lee-Chung Lu , Shyue-Shyh Lin , Li-Chun Tien
IPC分类号： H01L27/088
CPC分类号： H01L21/823475 , H01L21/76816 , H01L29/66545
摘要： A device includes a semiconductor substrate including an active region, a gate electrode directly over the active region, and a gate contact plug over and electrically coupled to the gate electrode. The gate contact plug includes at least a portion directly over, and vertically overlapping, the active region.
摘要翻译：一种器件包括半导体衬底，该半导体衬底包括有源区，直接在有源区上方的栅电极以及与该栅电极电连接的栅接触插塞。栅极接触插塞包括至少一个直接在有源区域上方并且垂直重叠的部分。

2. 发明授权

US09312260B2 Integrated circuits and manufacturing methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US09312260B2
公开(公告)日：2016-04-12
申请号：US13086186
申请日：2011-04-13
申请人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
发明人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
IPC分类号： H01L29/76 , H01L27/092 , H01L21/8238 , H01L23/485 , H01L27/02 , H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L27/092 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L29/0649 , H01L29/4238 , H01L29/495 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域分离。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属结构与第一源区电耦合。第二金属结构与第二漏区电耦合。第三金属结构设置在第一和第二金属结构之上并与第一和第二金属结构电耦合。第一金属结构体的宽度基本上等于或大于第三金属结构体的宽度。

3. 发明授权

US08431985B2 Layout and process of forming contact plugs 有权
标题翻译：形成接触塞的布局和工艺
公开(公告)号：US08431985B2
公开(公告)日：2013-04-30
申请号：US12852274
申请日：2010-08-06
申请人： Yung-Chin Hou , Lee-Chung Lu , Shyue-Shyh Lin , Li-Chun Tien
发明人： Yung-Chin Hou , Lee-Chung Lu , Shyue-Shyh Lin , Li-Chun Tien
IPC分类号： H01L29/66
CPC分类号： H01L21/823475 , H01L21/76816 , H01L29/66545
摘要： A device includes a semiconductor substrate including an active region, a gate electrode directly over the active region, and a gate contact plug over and electrically coupled to the gate electrode. The gate contact plug includes at least a portion directly over, and vertically overlapping, the active region.
摘要翻译：一种器件包括半导体衬底，该半导体衬底包括有源区，直接在有源区上方的栅电极以及与该栅电极电连接的栅接触插塞。栅极接触插塞包括至少一个直接在有源区域上方并且垂直重叠的部分。

4. 发明申请

US20120280287A1 Integrated Circuit Layouts with Power Rails under Bottom Metal Layer 有权
标题翻译：集成电路布局与底层金属层下的电源轨
公开(公告)号：US20120280287A1
公开(公告)日：2012-11-08
申请号：US13098925
申请日：2011-05-02
申请人： Yung-Chin Hou , Shyue-Shyh Lin , Li-Chun Tien , Shu-Min Chen , Pin-Dai Sue
发明人： Yung-Chin Hou , Shyue-Shyh Lin , Li-Chun Tien , Shu-Min Chen , Pin-Dai Sue
IPC分类号： H01L29/76 , H01L23/48
CPC分类号： H01L27/11807 , H01L23/5286 , H01L27/0207 , H01L2027/11881 , H01L2924/0002 , H01L2924/00
摘要： A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer.
摘要翻译：电路包括半导体衬底; 半导体衬底上的底部金属层，其中在半导体衬底和底部金属层之间没有附加的金属层; 以及在底部金属层下方包括插头级电源轨的电池。

5. 发明授权

US08507957B2 Integrated circuit layouts with power rails under bottom metal layer 有权
标题翻译：集成电路布局与底部金属层下的电源轨
公开(公告)号：US08507957B2
公开(公告)日：2013-08-13
申请号：US13098925
申请日：2011-05-02
申请人： Yung-Chin Hou , Shyue-Shyh Lin , Li-Chun Tien , Shu-Min Chen , Pin-Dai Sue
发明人： Yung-Chin Hou , Shyue-Shyh Lin , Li-Chun Tien , Shu-Min Chen , Pin-Dai Sue
IPC分类号： H01L23/48 , H01L21/768 , H01L29/41
CPC分类号： H01L27/11807 , H01L23/5286 , H01L27/0207 , H01L2027/11881 , H01L2924/0002 , H01L2924/00
摘要： A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer.
摘要翻译：电路包括半导体衬底; 半导体衬底上的底部金属层，其中在半导体衬底和底部金属层之间没有附加的金属层; 以及在底部金属层下方包括插头级电源轨的电池。

6. 发明申请

US20100281446A1 Integrated Circuit Design using DFM-Enhanced Architecture 有权
标题翻译：使用DFM增强架构的集成电路设计
公开(公告)号：US20100281446A1
公开(公告)日：2010-11-04
申请号：US12708242
申请日：2010-02-18
申请人： Yung-Chin Hou , Lee-Chung Lu , Li-Chun Tien , Yi-Kan Cheng , Chun-Hui Tai , Ta-Pen Guo , Yuan-Te Hou
发明人： Yung-Chin Hou , Lee-Chung Lu , Li-Chun Tien , Yi-Kan Cheng , Chun-Hui Tai , Ta-Pen Guo , Yuan-Te Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.
摘要翻译：集成电路库包括具有第一左边界和第一右边界的第一标准单元，以及具有第二左边界和第二右边界的第二标准单元。第一标准细胞和第二标准细胞具有相同的细胞变体。第一标准单元中的第一有源区具有与第二标准单元中的第二有源区不同的扩散长度。第一有源区和第二有源区是由表示第一标准单元和第二标准单元的相同电路图的相同分量表示的相应有源区。

7. 发明授权

US07821039B2 Layout architecture for improving circuit performance 有权
标题翻译：用于提高电路性能的布局架构
公开(公告)号：US07821039B2
公开(公告)日：2010-10-26
申请号：US12193354
申请日：2008-08-18
申请人： Li-Chun Tien , Lee-Chung Lu , Yung-Chin Hou , Chun-Hui Tai , Ta-Pen Guo , Sheng-Hsin Chen , Ping Chung Li
发明人： Li-Chun Tien , Lee-Chung Lu , Yung-Chin Hou , Chun-Hui Tai , Ta-Pen Guo , Sheng-Hsin Chen , Ping Chung Li
IPC分类号： H01L27/10 , H01L23/62 , H01L29/76 , H01L29/94 , H01L29/00
CPC分类号： H01L27/092 , H01L27/0207
摘要： An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.
摘要翻译：集成电路结构包括集成电路结构，其包括：包括第一栅电极的PMOS晶体管; 第一源区; 和第一漏区; 包括第二栅电极的NMOS晶体管，其中所述第一栅电极和所述第二栅电极是栅电极条的部分; 第二源区; 和第二漏区。在PMOS晶体管和NMOS晶体管之间不会形成附加的晶体管。集成电路还包括连接到第一源极区的VDD电源轨; 连接到第二源区的VSS电力轨; 以及电连接到栅电极条的互连端口。互连端口位于包括PMOS晶体管，NMOS晶体管以及PMOS晶体管和NMOS晶体管之间的区域的MOS对区域的外侧。 MOS对区域中的栅电极条的部分基本上是直的。

8. 发明申请

US20100196803A1 Methods for Cell Boundary Isolation in Double Patterning Design 有权
标题翻译：双重图案设计中细胞边界隔离的方法
公开(公告)号：US20100196803A1
公开(公告)日：2010-08-05
申请号：US12616970
申请日：2009-11-12
申请人： Lee-Chung Lu , Yi-Kan Cheng , Yuan-Te Hou , Yung-Chin Hou , Li-Chun Tien
发明人： Lee-Chung Lu , Yi-Kan Cheng , Yuan-Te Hou , Yung-Chin Hou , Li-Chun Tien
IPC分类号： G03F1/00 , G06F17/50
CPC分类号： G03F1/70 , G03F1/00
摘要： A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.
摘要翻译：设计用于芯片布局的双重图案掩模组的方法包括设计标准单元。在每个标准单元中，所有左边界图案被分配有第一指示符和第二指示符中的一个，并且所有右边图案都被分配有第一指示符和第二指示符中的另外一个。该方法还包括将标准单元放置在芯片布局的一行中。从行中的一个标准单元开始，标记单元的指示符更改在整行中传播。具有第一指示符的标准单元中的所有图案被转移到双图案掩模组的第一掩模。具有第二指示器的标准单元中的所有图案被转移到双重图案掩模组的第二掩模。

9. 发明申请

US20090315079A1 Layout Architecture for Improving Circuit Performance 有权
标题翻译：用于提高电路性能的布局架构
公开(公告)号：US20090315079A1
公开(公告)日：2009-12-24
申请号：US12193354
申请日：2008-08-18
申请人： Li-Chun Tien , Lee-Chung Lu , Yung-Chin Hou , Chun-Hui Tai , Ta-Pen Guo , Sheng-Hsin Chen , Ping Chung Li
发明人： Li-Chun Tien , Lee-Chung Lu , Yung-Chin Hou , Chun-Hui Tai , Ta-Pen Guo , Sheng-Hsin Chen , Ping Chung Li
IPC分类号： H01L21/8238
CPC分类号： H01L27/092 , H01L27/0207
摘要： An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.
摘要翻译：集成电路结构包括集成电路结构，其包括：包括第一栅电极的PMOS晶体管; 第一源区; 和第一漏区; 包括第二栅电极的NMOS晶体管，其中所述第一栅电极和所述第二栅电极是栅电极条的部分; 第二源区; 和第二漏区。在PMOS晶体管和NMOS晶体管之间不会形成附加的晶体管。集成电路还包括连接到第一源极区的VDD电源轨; 连接到第二源区的VSS电力轨; 以及电连接到栅电极条的互连端口。互连端口位于包括PMOS晶体管，NMOS晶体管以及PMOS晶体管和NMOS晶体管之间的区域的MOS对区域的外侧。 MOS对区域中的栅电极条的部分基本上是直的。

10. 发明授权

US08255837B2 Methods for cell boundary isolation in double patterning design 有权
标题翻译：双图案设计中单元边界隔离的方法
公开(公告)号：US08255837B2
公开(公告)日：2012-08-28
申请号：US12616970
申请日：2009-11-12
申请人： Lee-Chung Lu , Yi-Kan Cheng , Yuan-Te Hou , Yung-Chin Hou , Li-Chun Tien
发明人： Lee-Chung Lu , Yi-Kan Cheng , Yuan-Te Hou , Yung-Chin Hou , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F1/00
摘要： A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.
摘要翻译：设计用于芯片布局的双重图案掩模组的方法包括设计标准单元。在每个标准单元中，所有左边界图案被分配有第一指示符和第二指示符中的一个，并且所有右边图案都被分配有第一指示符和第二指示符中的另外一个。该方法还包括将标准单元放置在芯片布局的一行中。从行中的一个标准单元开始，标记单元的指示符更改在整行中传播。具有第一指示符的标准单元中的所有图案被转移到双图案掩模组的第一掩模。具有第二指示器的标准单元中的所有图案被转移到双重图案掩模组的第二掩模。

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