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1. 发明授权

US08671367B2 Integrated circuit design in optical shrink technology node 有权
标题翻译：光收缩技术节点集成电路设计
公开(公告)号：US08671367B2
公开(公告)日：2014-03-11
申请号：US12340294
申请日：2008-12-19
申请人： Chung-Hsing Wang , Lee-Chung Lu , Yung-Chin Hou , Lie-Szu Juang
发明人： Chung-Hsing Wang , Lee-Chung Lu , Yung-Chin Hou , Lie-Szu Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/505
摘要： Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files.
摘要翻译：公开了一种用于设计使用光收缩技术节点提供的电路和/或IC芯片的系统，方法和计算机可读介质。可以在第一技术节点中提供初始设计数据，并且通过在设计流程的一个或多个EDA工具中使用嵌入缩放因子，可以为光收缩技术节点中的电路生成设计（例如，掩模数据）。可以提供嵌入式缩放因子的EDA工具的示例是包括LPE卡片和RC提取技术文件的模拟模型和提取工具。

2. 发明授权

US08418112B2 Method of generating RC technology file 有权
标题翻译：生成RC技术文件的方法
公开(公告)号：US08418112B2
公开(公告)日：2013-04-09
申请号：US13039730
申请日：2011-03-03
申请人： Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng , Yung-Chin Hou
发明人： Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng , Yung-Chin Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5081
摘要： A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.
摘要翻译：公开了一种产生电阻 - 电容（RC）技术文件的方法。该方法包括从IC铸造接收多个金属方案并将多个金属方案分成一个或多个模块化RC组。该方法还包括识别模块化RC结构; 通过场解算器计算模块RC结构的电容值; 基于不具有互连的各种互连层计算RC结构的等效介电常数和等效高度; 计算所述多个金属方案中的每一种的等效介电常数和等效高度; 以及从所述模块化RC结构的电容值导出所述多个金属方案中的每一个的电容值。

3. 发明申请

US20120280287A1 Integrated Circuit Layouts with Power Rails under Bottom Metal Layer 有权
标题翻译：集成电路布局与底层金属层下的电源轨
公开(公告)号：US20120280287A1
公开(公告)日：2012-11-08
申请号：US13098925
申请日：2011-05-02
申请人： Yung-Chin Hou , Shyue-Shyh Lin , Li-Chun Tien , Shu-Min Chen , Pin-Dai Sue
发明人： Yung-Chin Hou , Shyue-Shyh Lin , Li-Chun Tien , Shu-Min Chen , Pin-Dai Sue
IPC分类号： H01L29/76 , H01L23/48
CPC分类号： H01L27/11807 , H01L23/5286 , H01L27/0207 , H01L2027/11881 , H01L2924/0002 , H01L2924/00
摘要： A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer.
摘要翻译：电路包括半导体衬底; 半导体衬底上的底部金属层，其中在半导体衬底和底部金属层之间没有附加的金属层; 以及在底部金属层下方包括插头级电源轨的电池。

4. 发明授权

US08261219B2 System on chip development with reconfigurable multi-project wafer technology 有权
标题翻译：系统片上开发与可重构多项目晶圆技术
公开(公告)号：US08261219B2
公开(公告)日：2012-09-04
申请号：US12133323
申请日：2008-06-04
申请人： Kun-Lung Chen , Shine Chien Chung , Yung-Chin Hou , Yu-Chun Wu
发明人： Kun-Lung Chen , Shine Chien Chung , Yung-Chin Hou , Yu-Chun Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.
摘要翻译：公开了一种在多工程晶片（MPW）上设计半导体电路的方法。首先确定由具有验证功能的一个或多个供应商设计的一个或多个标准模块。一些标准模块根据用途收费。通过使一个或多个连接通过一个或多个连接层来编程MPW的至少一个可重新配置的模块。根据电路的预定设计，标准模块还与编程的可重配置模块进一步连接。完成的电路然后被验证用于最终用途。

5. 发明申请

US20100281446A1 Integrated Circuit Design using DFM-Enhanced Architecture 有权
标题翻译：使用DFM增强架构的集成电路设计
公开(公告)号：US20100281446A1
公开(公告)日：2010-11-04
申请号：US12708242
申请日：2010-02-18
申请人： Yung-Chin Hou , Lee-Chung Lu , Li-Chun Tien , Yi-Kan Cheng , Chun-Hui Tai , Ta-Pen Guo , Yuan-Te Hou
发明人： Yung-Chin Hou , Lee-Chung Lu , Li-Chun Tien , Yi-Kan Cheng , Chun-Hui Tai , Ta-Pen Guo , Yuan-Te Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.
摘要翻译：集成电路库包括具有第一左边界和第一右边界的第一标准单元，以及具有第二左边界和第二右边界的第二标准单元。第一标准细胞和第二标准细胞具有相同的细胞变体。第一标准单元中的第一有源区具有与第二标准单元中的第二有源区不同的扩散长度。第一有源区和第二有源区是由表示第一标准单元和第二标准单元的相同电路图的相同分量表示的相应有源区。

6. 发明授权

US07821039B2 Layout architecture for improving circuit performance 有权
标题翻译：用于提高电路性能的布局架构
公开(公告)号：US07821039B2
公开(公告)日：2010-10-26
申请号：US12193354
申请日：2008-08-18
申请人： Li-Chun Tien , Lee-Chung Lu , Yung-Chin Hou , Chun-Hui Tai , Ta-Pen Guo , Sheng-Hsin Chen , Ping Chung Li
发明人： Li-Chun Tien , Lee-Chung Lu , Yung-Chin Hou , Chun-Hui Tai , Ta-Pen Guo , Sheng-Hsin Chen , Ping Chung Li
IPC分类号： H01L27/10 , H01L23/62 , H01L29/76 , H01L29/94 , H01L29/00
CPC分类号： H01L27/092 , H01L27/0207
摘要： An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.
摘要翻译：集成电路结构包括集成电路结构，其包括：包括第一栅电极的PMOS晶体管; 第一源区; 和第一漏区; 包括第二栅电极的NMOS晶体管，其中所述第一栅电极和所述第二栅电极是栅电极条的部分; 第二源区; 和第二漏区。在PMOS晶体管和NMOS晶体管之间不会形成附加的晶体管。集成电路还包括连接到第一源极区的VDD电源轨; 连接到第二源区的VSS电力轨; 以及电连接到栅电极条的互连端口。互连端口位于包括PMOS晶体管，NMOS晶体管以及PMOS晶体管和NMOS晶体管之间的区域的MOS对区域的外侧。 MOS对区域中的栅电极条的部分基本上是直的。

7. 发明申请

US20100196803A1 Methods for Cell Boundary Isolation in Double Patterning Design 有权
标题翻译：双重图案设计中细胞边界隔离的方法
公开(公告)号：US20100196803A1
公开(公告)日：2010-08-05
申请号：US12616970
申请日：2009-11-12
申请人： Lee-Chung Lu , Yi-Kan Cheng , Yuan-Te Hou , Yung-Chin Hou , Li-Chun Tien
发明人： Lee-Chung Lu , Yi-Kan Cheng , Yuan-Te Hou , Yung-Chin Hou , Li-Chun Tien
IPC分类号： G03F1/00 , G06F17/50
CPC分类号： G03F1/70 , G03F1/00
摘要： A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.
摘要翻译：设计用于芯片布局的双重图案掩模组的方法包括设计标准单元。在每个标准单元中，所有左边界图案被分配有第一指示符和第二指示符中的一个，并且所有右边图案都被分配有第一指示符和第二指示符中的另外一个。该方法还包括将标准单元放置在芯片布局的一行中。从行中的一个标准单元开始，标记单元的指示符更改在整行中传播。具有第一指示符的标准单元中的所有图案被转移到双图案掩模组的第一掩模。具有第二指示器的标准单元中的所有图案被转移到双重图案掩模组的第二掩模。

8. 发明申请

US20100095253A1 TABLE-BASED DFM FOR ACCURATE POST-LAYOUT ANALYSIS 有权
标题翻译：基于表的DFM用于精确的后布局分析
公开(公告)号：US20100095253A1
公开(公告)日：2010-04-15
申请号：US12250424
申请日：2008-10-13
申请人： Yung-Chin HOU , Ying-Chou CHENG , Ru-Gun LIU , Chih-Ming LAI , Yi-Kan CHENG , Chung-Kai LIN , Hsiao-Shu CHAO , Ping-Heng YEH , Min-Hong WU , Yao-Ching KU , Tsong-Hua OU
发明人： Yung-Chin HOU , Ying-Chou CHENG , Ru-Gun LIU , Chih-Ming LAI , Yi-Kan CHENG , Chung-Kai LIN , Hsiao-Shu CHAO , Ping-Heng YEH , Min-Hong WU , Yao-Ching KU , Tsong-Hua OU
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
摘要翻译：公开了一种用于集成电路设计和后期布局分析的系统和方法。集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。

9. 发明申请

US20090315079A1 Layout Architecture for Improving Circuit Performance 有权
标题翻译：用于提高电路性能的布局架构
公开(公告)号：US20090315079A1
公开(公告)日：2009-12-24
申请号：US12193354
申请日：2008-08-18
申请人： Li-Chun Tien , Lee-Chung Lu , Yung-Chin Hou , Chun-Hui Tai , Ta-Pen Guo , Sheng-Hsin Chen , Ping Chung Li
发明人： Li-Chun Tien , Lee-Chung Lu , Yung-Chin Hou , Chun-Hui Tai , Ta-Pen Guo , Sheng-Hsin Chen , Ping Chung Li
IPC分类号： H01L21/8238
CPC分类号： H01L27/092 , H01L27/0207
摘要： An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.
摘要翻译：集成电路结构包括集成电路结构，其包括：包括第一栅电极的PMOS晶体管; 第一源区; 和第一漏区; 包括第二栅电极的NMOS晶体管，其中所述第一栅电极和所述第二栅电极是栅电极条的部分; 第二源区; 和第二漏区。在PMOS晶体管和NMOS晶体管之间不会形成附加的晶体管。集成电路还包括连接到第一源极区的VDD电源轨; 连接到第二源区的VSS电力轨; 以及电连接到栅电极条的互连端口。互连端口位于包括PMOS晶体管，NMOS晶体管以及PMOS晶体管和NMOS晶体管之间的区域的MOS对区域的外侧。 MOS对区域中的栅电极条的部分基本上是直的。

10. 发明申请

US20050257177A1 System on chip development with reconfigurable multi-project wafer technology 有权
标题翻译：系统片上开发与可重构多项目晶圆技术
公开(公告)号：US20050257177A1
公开(公告)日：2005-11-17
申请号：US11119086
申请日：2005-04-29
申请人： Kun-Lung Chen , Shine Chung , Yung-Chin Hou , Yu-Chun Wu
发明人： Kun-Lung Chen , Shine Chung , Yung-Chin Hou , Yu-Chun Wu
IPC分类号： G06F7/00 , G06F17/50 , H03K19/177
CPC分类号： G06F17/5045
摘要： A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.
摘要翻译：公开了一种在多工程晶片（MPW）上设计半导体电路的方法。首先确定由具有验证功能的一个或多个供应商设计的一个或多个标准模块。一些标准模块根据用途收费。通过使一个或多个连接通过一个或多个连接层来编程MPW的至少一个可重新配置的模块。根据电路的预定设计，标准模块还与编程的可重配置模块进一步连接。完成的电路然后被验证用于最终用途。

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