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1. 发明授权

US08434032B2 Method of generating an intellectual property block design kit, method of generating an integrated circuit design, and simulation system for the integrated circuit design 有权
标题翻译：生成知识产权块设计套件的方法，集成电路设计的生成方法和集成电路设计的仿真系统
公开(公告)号：US08434032B2
公开(公告)日：2013-04-30
申请号：US12950371
申请日：2010-11-19
申请人： Lee-Chung Lu , Yun-Han Lee , Wei-Li Chen , Tan-Li Chou , Kheng-Guan Tan , Shi-Hung Wang
发明人： Lee-Chung Lu , Yun-Han Lee , Wei-Li Chen , Tan-Li Chou , Kheng-Guan Tan , Shi-Hung Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F2217/02 , G06F2217/66
摘要： The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for manufacturing an integrated circuit. According at least one embodiment, the IP block circuit design is generated. The IP block circuit design is simulated based on predetermined configuration sets, and each configuration set has manufacturing options and/or operating conditions. A plurality of system-level models for the predetermined configuration sets are generated based on the simulation of the IP block circuit design. The system-level characteristics table is generated by arranging the predetermined configuration sets and the system-level models in compliance with a system-level characteristics table template of a system-level characteristics modeling device. Then the IP block circuit design and the system-level characteristics table are stored as the IP block design kit.
摘要翻译：本申请公开了一种生成包括IP块电路设计和用于制造集成电路的系统级特性表的知识产权（IP）块设计套件的方法。根据至少一个实施例，产生IP块电路设计。 IP块电路设计基于预定的配置集进行仿真，每个配置集都具有制造选项和/或操作条件。基于IP块电路设计的仿真，生成用于预定配置集的多个系统级模型。通过根据系统级特征建模设备的系统级特征表模板布置预定配置集和系统级模型来生成系统级特征表。然后将IP块电路设计和系统级特性表存储为IP块设计工具包。

2. 发明授权

US08418111B2 Method and apparatus for achieving multiple patterning technology compliant design layout 有权
标题翻译：用于实现多种图案化技术兼容的设计布局的方法和装置
公开(公告)号：US08418111B2
公开(公告)日：2013-04-09
申请号：US12953661
申请日：2010-11-24
申请人： Huang-Yu Chen , Fang-Yu Fan , Yuan-Te Hou , Lee-Chung Lu , Ru-Gun Liu , Ken-Hsien Hsieh , Lee Fung Song , Wen-Chun Huang , Li-Chun Tien
发明人： Huang-Yu Chen , Fang-Yu Fan , Yuan-Te Hou , Lee-Chung Lu , Ru-Gun Liu , Ken-Hsien Hsieh , Lee Fung Song , Wen-Chun Huang , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G03F7/70433 , G03F7/70466
摘要： A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color.
摘要翻译：提供了一种用于实现多个图案化兼容技术设计布局的方法和装置。示例性方法包括提供具有路由轨迹的路由网格; 指定每个路线轨道至少两种颜色之一; 将具有多个特征的图案布局应用于所述路由网格，其中所述多个特征中的每一个对应于至少一个路由轨道; 以及应用特征分解约束来确定所述图案布局是否是符合多重图案化的布局。如果图案布局不是符合多重图案化的布局，则可以修改图案布局，直到实现多重图案化兼容布局。如果图案布局是符合多重图案化的布局，则该方法包括基于每个特征对应的至少一个路线轨迹的颜色来着色多个特征中的每一个，从而形成彩色图案布局，并且生成至少两个具有彩色图案布局的特点。每个面具都包含单一颜色的特征。

3. 发明授权

US08347132B2 System and method for reducing processor power consumption 有权
标题翻译：降低处理器功耗的系统和方法
公开(公告)号：US08347132B2
公开(公告)日：2013-01-01
申请号：US12619428
申请日：2009-11-16
申请人： Lee-Chung Lu , Chung-Hsing Wang , Myron Shak , Wei-Pin Changchien , Kuo-Yin Chen , Chi Wei Hu , Kevin Hung , Wu-An Kuo
发明人： Lee-Chung Lu , Chung-Hsing Wang , Myron Shak , Wei-Pin Changchien , Kuo-Yin Chen , Chi Wei Hu , Kevin Hung , Wu-An Kuo
IPC分类号： G06F1/00
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module.
摘要翻译：公开了一种用于减少处理器中的有功功率的系统和方法。方法实施例包括以下步骤：确定特定逻辑块何时不活动，确定特定逻辑块的供电状态，将特定逻辑块与主处理器内核隔离，以及断开特定逻辑块。当系统需要特定逻辑块时，该方法还包括重新激活该块。系统实施例包括耦合到时钟控制模块，隔离控制模块和报头/页脚模块的软件和处理器，其可操作以隔离特定逻辑块并关闭特定逻辑块，从而降低功率。另一个实施例包括通过时钟门控模块耦合到时钟的逻辑模块，用于隔离逻辑模块的隔离模块，用于禁止对逻辑模块供电的报头/页脚模块，以及用于控制时钟的电源和时钟门控控制模块门控模块和页眉/页脚模块。

4. 发明授权

US08255837B2 Methods for cell boundary isolation in double patterning design 有权
标题翻译：双图案设计中单元边界隔离的方法
公开(公告)号：US08255837B2
公开(公告)日：2012-08-28
申请号：US12616970
申请日：2009-11-12
申请人： Lee-Chung Lu , Yi-Kan Cheng , Yuan-Te Hou , Yung-Chin Hou , Li-Chun Tien
发明人： Lee-Chung Lu , Yi-Kan Cheng , Yuan-Te Hou , Yung-Chin Hou , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F1/00
摘要： A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.
摘要翻译：设计用于芯片布局的双重图案掩模组的方法包括设计标准单元。在每个标准单元中，所有左边界图案被分配有第一指示符和第二指示符中的一个，并且所有右边图案都被分配有第一指示符和第二指示符中的另外一个。该方法还包括将标准单元放置在芯片布局的一行中。从行中的一个标准单元开始，标记单元的指示符更改在整行中传播。具有第一指示符的标准单元中的所有图案被转移到双图案掩模组的第一掩模。具有第二指示器的标准单元中的所有图案被转移到双重图案掩模组的第二掩模。

5. 发明授权

US08239806B2 Routing system and method for double patterning technology 有权
标题翻译：双重图案化技术的路由系统和方法
公开(公告)号：US08239806B2
公开(公告)日：2012-08-07
申请号：US12649979
申请日：2009-12-30
申请人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Yuan-Te Hou , Gwan Sin Chang , Wen-Ju Yang , Zhe-Wei Jiang , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.
摘要翻译：一种方法包括接收要包括在IC布局中的多个电路部件的标识。生成表示连接两个电路部件的第一图案的数据。第一图案具有多个片段。至少两个片段具有彼此垂直的纵向方向。保留与至少两个段中的至少一个相邻的至少一个无图案区域。生成表示在第一图案附近的一个或多个附加图案的数据。在无模式区域中没有形成附加图案。第一种图案和附加图案形成双重图案化顺应的图案集合。将双图案化顺应的图案集合输出到机器可读存储介质，以由用于控制制造用于使用双重图案化技术图案化半导体衬底的一对掩模的工艺的系统读取。

6. 发明授权

US08227869B2 Performance-aware logic operations for generating masks 有权
标题翻译：用于生成掩码的性能感知逻辑操作
公开(公告)号：US08227869B2
公开(公告)日：2012-07-24
申请号：US13284594
申请日：2011-10-28
申请人： Lee-Chung Lu , Chung-Te Lin , Yen-Sen Wang , Yao-Jen Chuang , Gwan Sin Chang
发明人： Lee-Chung Lu , Chung-Te Lin , Yen-Sen Wang , Yao-Jen Chuang , Gwan Sin Chang
IPC分类号： H01L21/70 , H01L27/088 , H01L29/76
CPC分类号： G06F17/5068 , G03F1/36
摘要： Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules.
摘要翻译：通过PMOS器件上的压应力层获得用于PMOS和NMOS器件的应力工程，其中当从顶部向下观察时，压应力层具有多边形的形状，并且其中多边形包括限定在其周边的凹部。 NMOS器件具有拉伸应力层，其中从顶部向下观察时，拉伸应力层具有多边形的形状，其中多边形包括在其周边的突起，突出部延伸到第一应力层的凹部中。因此，可以在不违反设计规则的情况下改善两种装置的应力性能。

7. 发明授权

US08122394B2 Performance-aware logic operations for generating masks 有权
标题翻译：用于生成掩码的性能感知逻辑操作
公开(公告)号：US08122394B2
公开(公告)日：2012-02-21
申请号：US12212088
申请日：2008-09-17
申请人： Lee-Chung Lu , Chung-Te Lin , Yen-Sen Wang , Yao-Jen Chuang , Gwan Sin Chang
发明人： Lee-Chung Lu , Chung-Te Lin , Yen-Sen Wang , Yao-Jen Chuang , Gwan Sin Chang
IPC分类号： G06F17/50 , G06F7/66 , G06K9/00 , H01L21/66
CPC分类号： G06F17/5068 , G03F1/36
摘要： A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks.
摘要翻译：用于形成用于制造电路的掩模的方法包括提供电路的设计，其中电路包括器件; 执行第一逻辑操作以确定用于形成所述设备的第一特征的第一区域; 以及执行第二逻辑操作以将所述第一特征扩展到大于所述第一区域的第二区域。可以使用第二区域的图案来形成掩模。

8. 发明授权

US07966596B2 Place-and-route layout method with same footprint cells 有权
标题翻译：具有相同占位面积单元格的布局和布局方法
公开(公告)号：US07966596B2
公开(公告)日：2011-06-21
申请号：US12199617
申请日：2008-08-27
申请人： Lee-Chung Lu , Chung-Hsing Wang , Ping Chung Li , Chun-Hui Tai , Li-Chun Tien , Gwan Sin Chang
发明人： Lee-Chung Lu , Chung-Hsing Wang , Ping Chung Li , Chun-Hui Tai , Li-Chun Tien , Gwan Sin Chang
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F17/5077
摘要： This invention discloses a method for automatically generating an integrated circuit (IC) layout, the method comprises determining a first cell height, creating a plurality of standard cells all having the first cell height, and generating the IC layout from the plurality of standard cells by placing and routing thereof.
摘要翻译：本发明公开了一种自动生成集成电路（IC）布局的方法，该方法包括：确定第一单元高度，创建全部具有第一单元高度的多个标准单元，以及通过以下步骤从多个标准单元生成IC布局放置和布线。

9. 发明申请

US20110072405A1 Chip-Level ECO Shrink 有权
标题翻译：芯片级ECO收缩
公开(公告)号：US20110072405A1
公开(公告)日：2011-03-24
申请号：US12831982
申请日：2010-07-07
申请人： Huang-Yu Chen , Ho Che Yu , Chung-Hsing Wang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
发明人： Huang-Yu Chen , Ho Che Yu , Chung-Hsing Wang , Hsiao-Shu Chao , Yi-Kan Cheng , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/0207
摘要： In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.
摘要翻译：在形成集成电路的方法中，提供包括第一知识产权（IP）的芯片表示的布局。生成与第一个IP重叠并从第一个IP边缘延伸出来的切割线。切割线将芯片表示划分成多个电路区域。多个电路区域相对于第一IP的位置向外偏移以产生空间。第一个IP被吹入空间，产生一个IP地址。然后执行直接收缩。

10. 发明申请

US20100293514A1 DESIGN-DRIVEN METAL CRITICAL DIMENSION (CD) BIASING 有权
标题翻译：设计驱动金属关键尺寸（CD）偏移
公开(公告)号：US20100293514A1
公开(公告)日：2010-11-18
申请号：US12464578
申请日：2009-05-12
申请人： Louis Chao-Chiuan Liu , Lee-Chung Lu , Yao-Ching Ku
发明人： Louis Chao-Chiuan Liu , Lee-Chung Lu , Yao-Ching Ku
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5031 , G06F17/5036 , G06F17/5077 , G06F2217/84
摘要： A method of designing an integrated circuit (“IC”) is provided that includes placing an IC design, where the IC design includes a first element, a second element, and a path coupling the first and second elements, and routing the IC design. Further, the method includes obtaining at least one of resistivity data and capacitance data related to the path, and obtaining timing data related to the path. The method also includes using at least one of the resistivity data, the capacitance data, and the timing data to determine a critical dimension (“CD”) bias to be applied to the path, and modifying the IC design, where modifying includes applying the CD bias to the path.
摘要翻译：提供一种设计集成电路（“IC”）的方法，其包括放置IC设计，其中IC设计包括第一元件，第二元件和耦合第一和第二元件的路径，以及布线IC设计。此外，该方法包括获得与路径相关的电阻率数据和电容数据中的至少一个，并获得与该路径相关的定时数据。该方法还包括使用电阻率数据，电容数据和定时数据中的至少一个来确定要施加到路径的临界尺寸（“CD”）偏差，以及修改IC设计，其中修改包括应用 CD偏向路径。

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