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51. 发明授权

US08220068B2 Monolithic high aspect ratio nano-size scanning probe microscope (SPM) tip formed by nanowire growth 有权
标题翻译：通过纳米线生长形成的单片高宽比纳米尺寸扫描探针显微镜（SPM）尖端
公开(公告)号：US08220068B2
公开(公告)日：2012-07-10
申请号：US12533427
申请日：2009-07-31
申请人： Guy M. Cohen , Hendrik F. Hamann
发明人： Guy M. Cohen , Hendrik F. Hamann
IPC分类号： G01Q70/12
CPC分类号： G01Q70/12 , G01Q60/22
摘要： A scanning probe where the micromachined pyramid tip is extended by the growth of an epitaxial nanowire from the top portion of the tip is disclosed. A metallic particle, such as gold, may terminate the nanowire to realize an apertureless near-field optical microscope probe.
摘要翻译：公开了一种扫描探针，其中微加工金字塔尖端通过外延纳米线从尖端的顶部生长而延伸。诸如金的金属颗粒可以终止纳米线以实现无孔近场光学显微镜探针。

52. 发明授权

US07999251B2 Nanowire MOSFET with doped epitaxial contacts for source and drain 有权
标题翻译：具有用于源极和漏极的掺杂外延触点的纳米线MOSFET
公开(公告)号：US07999251B2
公开(公告)日：2011-08-16
申请号：US11519176
申请日：2006-09-11
申请人： Jack O. Chu , Guy M. Cohen , John A. Ott , Michael J. Rooks , Paul M. Solomon
发明人： Jack O. Chu , Guy M. Cohen , John A. Ott , Michael J. Rooks , Paul M. Solomon
IPC分类号： H01L29/775 , H01L29/786
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/458 , H01L29/7839 , H01L29/785 , H01L29/78618 , H01L29/78684 , H01L29/78696
摘要： A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.
摘要翻译：公开了具有形成FET沟道的纳米线的FET结构以及由纳米线体径向外延形成的掺杂源极和漏极区。讨论了顶盖门控和底部门控纳米线FET结构。源极和漏极制造可以使用选择性或非选择性外延。

53. 发明授权

US07749905B2 Vertical Fet with nanowire channels and a silicided bottom contact 失效
标题翻译：垂直Fet与纳米线通道和硅底部接触
公开(公告)号：US07749905B2
公开(公告)日：2010-07-06
申请号：US12167686
申请日：2008-07-03
申请人： Guy M. Cohen , Paul M. Solomon
发明人： Guy M. Cohen , Paul M. Solomon
IPC分类号： H01L21/44
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/0237 , H01L21/02381 , H01L21/02433 , H01L21/02521 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02645 , H01L21/02653 , H01L29/045 , H01L29/0676 , H01L29/66666 , H01L29/7827 , H01L29/7828 , Y10S977/762 , Y10S977/938
摘要： A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.
摘要翻译：公开了一种具有形成FET沟道的纳米线的垂直FET结构。纳米线形成在导电硅化物层上。纳米线由周围的门浇口。顶部和底部绝缘体插塞用作栅极间隔，并减少栅极 - 源极和栅极 - 漏极电容。

54. 发明申请

US20080164495A1 HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) WITH SELF-ALIGNED SUB-LITHOGRAPHIC METAL-SEMICONDUCTOR ALLOY BASE CONTACTS 有权
标题翻译：具有自对准亚垂直金属 - 半导体合金基底接触的异相双极晶体管（HBT）
公开(公告)号：US20080164495A1
公开(公告)日：2008-07-10
申请号：US11621864
申请日：2007-01-10
申请人： Guy M. Cohen , Francois Pagette
发明人： Guy M. Cohen , Francois Pagette
IPC分类号： H01L29/737 , H01L21/04
CPC分类号： H01L29/737 , H01L29/1004 , H01L29/66242
摘要： A heterojunction bipolar transistor structure with self-aligned sub-lithographic extrinsic base region including a self-aligned metal-semiconductor alloy and self-aligned metal contacts made to the base is disclosed. The lateral dimension of the extrinsic base region is defined by the footprint of a sacrificial spacer, and its thickness is controlled by selective epitaxy. A self-aligned semiconductor-metal alloy and self-aligned metal contacts are made to the extrinsic base using a method compatible with conventional silicon processing.
摘要翻译：公开了一种异质结双极晶体管结构，其具有包括自对准金属半导体合金和自底向金属触点的自对准亚光刻非本征基极区域。外部基极区域的横向尺寸由牺牲间隔物的覆盖层限定，并且其厚度通过选择性外延进行控制。使用与常规硅处理兼容的方法，将非对准半导体 - 金属合金和自对准金属接触制成外部基极。

55. 发明授权

US07315065B2 Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates 有权
标题翻译：用于制造绝缘体上硅（SGOI）和绝缘体上（GeI）绝缘体（GOI）基板的方法
公开(公告)号：US07315065B2
公开(公告)日：2008-01-01
申请号：US11481525
申请日：2006-07-06
申请人： Tze-chiang Chen , Guy M. Cohen , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Tze-chiang Chen , Guy M. Cohen , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L29/12 , H01L31/036 , H01L71/01 , H01L71/12 , H01L31/309
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

56. 发明授权

US07125785B2 Mixed orientation and mixed material semiconductor-on-insulator wafer 有权
标题翻译：混合取向和混合材料绝缘体上半导体晶片
公开(公告)号：US07125785B2
公开(公告)日：2006-10-24
申请号：US10865920
申请日：2004-06-14
申请人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
发明人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
IPC分类号： H01L21/20
CPC分类号： H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.
摘要翻译：本公开通常涉及具有包括混合单晶取向区域和/或混合单晶半导体材料区域的平坦化表面的半导体衬底，其中每个区域是电隔离的。根据本公开的一个实施例，SOI区域上的CMOS器件在具有不同取向的半导体上制造。根据另一实施例，SOI器件被认为具有多个具有不同半导体材料，晶格常数或晶格应变中的至少一个的半导体区域。还公开了用于制造本发明的不同实施例的方法和过程。

57. 发明授权

US07101762B2 Self-aligned double gate mosfet with separate gates 失效
标题翻译：自对准双门mosfet与分离的门
公开(公告)号：US07101762B2
公开(公告)日：2006-09-05
申请号：US11050366
申请日：2005-02-03
申请人： Guy M. Cohen , Hon-Sum P. Wong
发明人： Guy M. Cohen , Hon-Sum P. Wong
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A structure and method of manufacturing a double-gate integrated circuit which includes forming a laminated structure having a channel layer and first insulating layers on each side of the channel layer, forming openings in the laminated structure, forming drain and source regions in the openings, removing portions of the laminated structure to leave a first portion of the channel layer exposed, forming a first gate dielectric layer on the channel layer, forming a first gate electrode on the first gate dielectric layer, removing portions of the laminated structure to leave a second portion of the channel layer exposed, forming a second gate dielectric layer on the channel layer, forming a second gate electrode on the second gate dielectric layer, doping the drain and source regions, using self-aligned ion implantation, wherein the first gate electrode and the second gate electrode are formed independent of each other.
摘要翻译：一种制造双栅极集成电路的结构和方法，包括在沟道层的每一侧上形成具有沟道层和第一绝缘层的层叠结构，在层叠结构中形成开口，在开口中形成漏极和源极区域，去除所述层叠结构的部分以使所述沟道层的第一部分暴露，在所述沟道层上形成第一栅极电介质层，在所述第一栅极介电层上形成第一栅电极，去除所述层叠结构的部分以留下第二栅极电介质层在所述沟道层上形成第二栅极电介质层，在所述第二栅极电介质层上形成第二栅极电极，使用自对准离子注入来掺杂所述漏极和源极区域，其中所述第一栅电极和第二栅电极彼此独立地形成。

58. 发明授权

US06365465B1 Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques 失效
标题翻译：通过选择性外延和硅晶片结合技术的自对准双栅极MOSFET
公开(公告)号：US06365465B1
公开(公告)日：2002-04-02
申请号：US09272297
申请日：1999-03-19
申请人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
发明人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
IPC分类号： H01L21336
CPC分类号： H01L29/78654 , H01L21/76251 , H01L21/76264 , H01L21/76275 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/78648 , H01L29/78684 , H01L29/78687 , H01L29/78696
摘要： A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.
摘要翻译：制造双栅极金属氧化物半导体晶体管的结构和方法包括在单晶硅沟道的每一侧上形成具有单晶硅沟道层和绝缘氧化物层和氮化物层的叠层结构，在层叠结构中形成开口，在开口中形成漏极和源极区域，掺杂漏极和源极区域，在层压结构上形成掩模，去除未被掩模保护的层压结构的部分，去除掩模和绝缘氧化物和氮化物层以留下单个从漏极和源极区域悬置的晶体硅沟道层，形成覆盖漏极和源极区域和沟道层的氧化物层，以及在氧化物层上形成双栅极导体，使得双栅极导体包括第一导体在单晶硅沟道层的第一侧和在单晶的第二面上的第二导体 l硅通道层。

59. 发明授权

US08440999B2 Semiconductor chip with graphene based devices in an interconnect structure of the chip 有权
标题翻译：半导体芯片采用基于石墨烯的器件，在芯片的互连结构中
公开(公告)号：US08440999B2
公开(公告)日：2013-05-14
申请号：US13027797
申请日：2011-02-15
申请人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-yung Sung
发明人： Christos D. Dimitrakopoulos , Guy M. Cohen , Stephen M. Gates , Alfred Grill , Timothy J. McArdle , Chun-yung Sung
IPC分类号： H01L29/78
CPC分类号： H01L21/02527 , H01L29/1606 , H01L29/41766 , H01L29/42356 , H01L29/66431 , H01L29/778 , H01L2924/00013 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device.
摘要翻译：半导体结构包括包含其中包含的至少一个第一导电区域的第一电介质材料。该结构还包括位于第一介电材料顶部的至少一个含石墨烯的半导体器件。所述至少一个含石墨烯的半导体器件包括覆盖并与第一导电区直接相连的石墨烯层。所述结构还包括覆盖所述至少一个含石墨烯的半导体器件和所述第一电介质材料的部分的第二电介质材料。第二电介质材料包括其中包含的至少一个第二导电区域，并且所述至少一个第二导电区域与所述至少一个含石墨烯的半导体器件的导电元件接触。

60. 发明申请

US20130019351A1 PRODUCTION SCALE FABRICATION METHOD FOR HIGH RESOLUTION AFM TIPS 有权
标题翻译：高分辨率AFM提示的生产规模制作方法
公开(公告)号：US20130019351A1
公开(公告)日：2013-01-17
申请号：US13608372
申请日：2012-09-10
申请人： Guy M. Cohen , Mark C. Reuter , Brent A. Wacaser , Maha M. Khayyat
发明人： Guy M. Cohen , Mark C. Reuter , Brent A. Wacaser , Maha M. Khayyat
IPC分类号： G01Q60/38 , G01Q60/40 , B82Y15/00
CPC分类号： G01Q70/12 , G01Q60/38
摘要： A high resolution AFM tip is provided which includes an AFM probe including a semiconductor cantilever having a semiconductor pyramid extending upward from a surface of the semiconductor cantilever, the semiconductor pyramid having an apex. The AFM tip also includes a single Al-doped semiconductor nanowire on the exposed apex of the semiconductor pyramid, wherein the single Al-doped semiconductor nanowire is epitaxial with respect to the apex of the semiconductor pyramid.
摘要翻译：提供了一种高分辨率AFM尖端，其包括AFM探针，其包括具有从半导体悬臂的表面向上延伸的半导体金字塔的半导体悬臂，所述半导体金字塔具有顶点。 AFM尖端还包括在半导体金字塔的暴露的顶点上的单个Al掺杂的半导体纳米线，其中单个Al掺杂的半导体纳米线相对于半导体金字塔的顶点是外延的。

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