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1. 发明授权

US08785281B2 CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials 失效
标题翻译： CMOS结构及其制造方法，使用多个晶体取向和栅极材料
公开(公告)号：US08785281B2
公开(公告)日：2014-07-22
申请号：US13369707
申请日：2012-02-09
申请人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
发明人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/8234
CPC分类号： H01L21/28079 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/6659
摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.
摘要翻译：制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。平坦化层位于第二栅极材料层上。平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。也可以在第一栅极叠层上形成蚀刻停止层。所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

2. 发明申请

US20130298971A1 COST-EFFICENT HIGH POWER PECVD DEPOSITION FOR SOLAR CELLS 审中-公开
标题翻译：太阳能电池的成本效益高功率PECVD沉积
公开(公告)号：US20130298971A1
公开(公告)日：2013-11-14
申请号：US13468292
申请日：2012-05-10
申请人： Tze-Chiang Chen , Augustin J. Hong , Jeehwan Kim , Devendra K. Sadana
发明人： Tze-Chiang Chen , Augustin J. Hong , Jeehwan Kim , Devendra K. Sadana
IPC分类号： H01L31/02 , H01L31/0376 , C23C16/50 , H01L31/036
CPC分类号： H01L31/077 , C23C16/0272 , C23C16/45523 , C23C16/45557 , C23C16/50 , C23C16/515 , H01L21/02532 , H01L21/0262 , H01L31/02167 , H01L31/022466 , H01L31/022475 , H01L31/022483 , H01L31/03682 , H01L31/03687 , H01L31/03762 , H01L31/03921 , H01L31/056 , H01L31/065 , H01L31/1816 , H01L31/20 , Y02E10/52 , Y02E10/546 , Y02E10/548
摘要： A method for forming a photovoltaic device includes providing a substrate. A layer is deposited to form one or more layers of a photovoltaic stack on the substrate. The depositing of the amorphous layer includes performing a high power flash deposition for depositing a first portion of the layer. A low power deposition is performed for depositing a second portion of the layer.
摘要翻译：一种形成光伏器件的方法包括提供衬底。沉积层以在衬底上形成一层或多层光伏堆叠。非晶层的沉积包括执行大功率闪蒸沉积以沉积该层的第一部分。执行低功率沉积以沉积该层的第二部分。

3. 发明授权

US08138574B2 PCM with poly-emitter BJT access devices 有权
标题翻译： PCM与多发射器BJT接入设备
公开(公告)号：US08138574B2
公开(公告)日：2012-03-20
申请号：US12510588
申请日：2009-07-28
申请人： Tze-Chiang Chen , Chung Hon Lam , Bipin Rajendran
发明人： Tze-Chiang Chen , Chung Hon Lam , Bipin Rajendran
IPC分类号： H01L27/06
CPC分类号： H01L45/1233 , H01L27/2445 , H01L27/2463 , H01L45/06
摘要： A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. A memory cell for a phase change memory (PCM) includes a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor.
摘要翻译：相变存储器（PCM）包括包括多个存储器单元的阵列，包括相变元件（PCE）的存储单元; 以及包括双极结型晶体管（BJT）的PCE存取装置，所述BJT包括包含多晶半导体的发射极区域。用于相变存储器（PCM）的存储单元包括相变元件（PCE）; 以及包括双极结型晶体管（BJT）的PCE存取装置，所述BJT包括包含多晶半导体的发射极区域。

4. 发明申请

US20110298060A1 INTERFACE STRUCTURE FOR CHANNEL MOBILITY IMPROVEMENT IN HIGH-K METAL GATE STACK 有权
标题翻译：用于高K金属门盖的通道移动性改进的界面结构
公开(公告)号：US20110298060A1
公开(公告)日：2011-12-08
申请号：US12792242
申请日：2010-06-02
申请人： Tze-Chiang Chen , Dechao Guo , Philip J. Oldiges , Yanfeng Wang
发明人： Tze-Chiang Chen , Dechao Guo , Philip J. Oldiges , Yanfeng Wang
IPC分类号： H01L29/423 , H01L21/28
CPC分类号： H01L29/517 , H01L21/28176 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/51 , H01L29/513 , H01L29/518
摘要： A gate stack structure for field effect transistor (FET) devices includes a nitrogen rich first dielectric layer formed over a semiconductor substrate surface; a nitrogen deficient, oxygen rich second dielectric layer formed on the nitrogen rich first dielectric layer, the first and second dielectric layers forming, in combination, a bi-layer interfacial layer; a high-k dielectric layer formed over the bi-layer interfacial layer; a metal gate conductor layer formed over the high-k dielectric layer; and a work function adjusting dopant species diffused within the high-k dielectric layer and within the nitrogen deficient, oxygen rich second dielectric layer, and wherein the nitrogen rich first dielectric layer serves to separate the work function adjusting dopant species from the semiconductor substrate surface.
摘要翻译：用于场效应晶体管（FET）器件的栅极堆叠结构包括形成在半导体衬底表面上的富氮第一介电层; 形成在富氮第一介电层上的缺氮富氧的第二电介质层，第一和第二电介质层组合形成双层界面层; 形成在双层界面层上的高k电介质层; 形成在高k电介质层上的金属栅极导体层; 以及调节掺杂物质的功函数，其在所述高k电介质层内和所述缺氮富氧的第二电介质层内扩散，并且其中所述富氮第一介电层用于将所述功函数调节掺杂剂物质与所述半导体衬底表面分离。

5. 发明授权

US07847356B2 Metal gate high-K devices having a layer comprised of amorphous silicon 有权
标题翻译：具有由非晶硅组成的层的金属栅极高K器件
公开(公告)号：US07847356B2
公开(公告)日：2010-12-07
申请号：US12542855
申请日：2009-08-18
申请人： Tze-Chiang Chen , Bruce B. Doris , Vijay Narayanan , Vamsi Paruchuri
发明人： Tze-Chiang Chen , Bruce B. Doris , Vijay Narayanan , Vamsi Paruchuri
IPC分类号： H01L27/088 , H01L27/092 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/823857 , H01L21/823878 , H01L29/517
摘要： Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.
摘要翻译：公开了一种制造半导体器件的方法，以及根据该方法制造的器件。该方法包括提供由硅构成的衬底; 执行浅沟槽隔离工艺以描绘nFET和pFET有源区域，并且在每个有源区域内，在衬底的表面上形成栅极结构，所述栅极结构从衬底的表面依次包括高介电常数氧化物，由金属构成的层，由非晶硅构成的层以及由多晶硅构成的层。提供由非晶硅组成的层，以至少在多晶硅层和/或金属层的沉积和加工过程中基本上防止高介电常数氧化物层在垂直方向上的再生长。

6. 发明授权

US07138319B2 Deep trench isolation of embedded DRAM for improved latch-up immunity 失效
公开(公告)号：US07138319B2
公开(公告)日：2006-11-21
申请号：US10905538
申请日：2005-01-10
申请人： Tze-Chiang Chen , Kiang-Kai Han
发明人： Tze-Chiang Chen , Kiang-Kai Han
IPC分类号： H01L21/336
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/76232 , H01L27/10829 , H01L27/10897
摘要： A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.

7. 发明申请

US20060249790A1 Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-inulator (GOI) substrates 有权
标题翻译：用于制造绝缘体上硅（SGOI）和Ge-in-inulator（GOI）基板的方法
公开(公告)号：US20060249790A1
公开(公告)日：2006-11-09
申请号：US11481525
申请日：2006-07-06
申请人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

8. 发明授权

US06955926B2 Method of fabricating data tracks for use in a magnetic shift register memory device 失效
标题翻译：制造用于磁移位寄存器存储器件的数据轨道的方法
公开(公告)号：US06955926B2
公开(公告)日：2005-10-18
申请号：US10788190
申请日：2004-02-25
申请人： Tze-chiang Chen , Stuart S. P. Parkin
发明人： Tze-chiang Chen , Stuart S. P. Parkin
IPC分类号： G11C11/15 , G11C19/02 , G11C19/08 , H01L21/00
CPC分类号： G11C19/02 , G11C19/0841
摘要： A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/or silicon layers. Vias of approximately 10 microns tall with a cross-section on the order of 100 nm×100 nm are etched in this multilayered stack of alternating layers. Vias may be etched form smooth or notched walls. Vias are filled by electroplating layers of alternating types of ferromagnetic or ferrimagnetic metals. The alternating ferromagnetic or ferrimagnetic layers are comprised of magnetic materials with different magnetization or magnetic exchange or magnetic anisotropies. These different magnetic characteristics allow the pinning of magnetic domain walls at the boundaries between these layers. Alternatively, vias are filled with a homogeneous ferromagnetic material. Magnetic domain walls are formed by the discontinuity in the ferromagnetic or ferromagnetic material that occurs at the notches or at the protuberances along the via walls.
摘要翻译：用于磁移位寄存器存储器系统的磁数据磁道可以通过形成交替的电介质层和/或硅层的多层叠层来制造。在该多层交替层中蚀刻约10微米高的具有100nm×100nm量级的横截面的通孔。通孔可能被蚀刻形成平滑或缺口的墙壁。通孔由交替类型的铁磁或亚铁磁性金属的电镀层填充。交替的铁磁或亚铁磁层由具有不同磁化或磁交换或磁各向异性的磁性材料组成。这些不同的磁特性允许磁畴壁在这些层之间的边界处的钉扎。或者，通孔用均匀的铁磁材料填充。磁畴壁由铁氧体或铁磁材料中的不连续部分形成，这些不规则发生在沿着通孔壁的凹口或凸起处。

9. 发明申请

US20050106836A1 DEEP TRENCH ISOLATION OF EMBEDDED DRAM FOR IMPROVED LATCH-UP IMMUNITY 失效
标题翻译：嵌入式DRAM的DEEP TRENCH隔离改进的LATCH-UP免疫
公开(公告)号：US20050106836A1
公开(公告)日：2005-05-19
申请号：US10905538
申请日：2005-01-10
申请人： Tze-Chiang Chen , Liang-Kai Han
发明人： Tze-Chiang Chen , Liang-Kai Han
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/08 , H01L27/092 , H01L27/108
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/76232 , H01L27/10829 , H01L27/10897
摘要： A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic circuit region of the semiconductor device, the deep trench isolation being filled with an insulative material. The deep trench isolation thereby prevents the propagation of crystal defects generated in the logic circuit region from propagating into the memory storage region.
摘要翻译：公开了一种用于阻止在半导体器件中产生的缺陷传播的保护结构。在示例性实施例中，该结构包括在半导体器件的存储器存储区域和半导体器件的逻辑电路区域之间形成的深沟槽隔离，深沟槽隔离件填充有绝缘材料。深沟槽隔离从而防止在逻辑电路区域中产生的晶体缺陷的传播不会传播到存储器存储区域中。

10. 发明授权

US5106767A Process for fabricating low capacitance bipolar junction transistor 失效
标题翻译：制造低电容双极结型晶体管的工艺
公开(公告)号：US5106767A
公开(公告)日：1992-04-21
申请号：US683408
申请日：1991-04-10
申请人： Janes H. Comfort , Tze-Chiang Chen , Pong-Fei Lu , Bernard S. Meyerson , Yuan-Chen Sun , Denny D. Tang
发明人： Janes H. Comfort , Tze-Chiang Chen , Pong-Fei Lu , Bernard S. Meyerson , Yuan-Chen Sun , Denny D. Tang
IPC分类号： H01L21/285 , H01L21/331 , H01L21/762
CPC分类号： H01L29/66287 , H01L21/28525 , H01L21/76229 , H01L29/66242 , Y10S148/102 , Y10S148/117 , Y10S148/124
摘要： This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-algined elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device. The last mentioned oxide layer starts out early in the fabrication process as a layer of oxidizable material, preferably polycrystalline silicon, which, at later steps in the process, acts as an etch-stop in its unoxidized state and as a memory element and mask in its oxidized state when a self-aligned datum element is removed and the thus exposed underlying dielectric elements must be removed to provide a planar emitter opening. The resulting transistor includes a planar emitter-emitter contact interface which provides for fine control of emitter depth in the underlying intrinsic base region.
摘要翻译：本发明涉及一种双极晶体管，其在升高的基极方面包含发射极，集电极基座以及所有这些基底都是自对准的内在和外在基极。本发明还涉及一种用于制造这样的器件的方法，其使用单个光刻和掩蔽步骤获得上述元件的自对准。晶体管的结构除了具有自嵌入元件之外，还包括复合介电隔离层，其不仅允许在器件制造期间执行多种功能，而且还可以在器件操作期间提供期望的电特性。复合隔离层由邻近半导体表面的氧化物层组成; 氧化物层上的氮化物层和该器件的最终结构中的氮化物层上的氧化物层。最后提到的氧化物层在制造过程的早期开始为可氧化材料层，优选多晶硅，其在该工艺的后续步骤中用作其未氧化状态的蚀刻停止，并且作为存储元件和掩模当自对准基准元件被去除并且必须去除这样暴露的下面的介质元件以提供平面发射器开口时，其氧化态。所产生的晶体管包括平面的发射极 - 发射极接触界面，其提供对底层本征基极区域的发射极深度的精细控制。

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