专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080251880A1 MIXED ORIENTATION AND MIXED MATERIAL SEMICONDUCTOR-ON-INSULATOR WAFER 审中-公开
标题翻译：混合方向和混合材料半导体绝缘体波形
公开(公告)号：US20080251880A1
公开(公告)日：2008-10-16
申请号：US12099016
申请日：2008-04-07
申请人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
发明人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
IPC分类号： H01L21/20 , H01L29/04
CPC分类号： H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.
摘要翻译：本公开通常涉及具有包括混合单晶取向区域和/或混合单晶半导体材料区域的平坦化表面的半导体衬底，其中每个区域是电隔离的。根据本公开的一个实施例，SOI区域上的CMOS器件在具有不同取向的半导体上制造。根据另一实施例，SOI器件被认为具有多个具有不同半导体材料，晶格常数或晶格应变中的至少一个的半导体区域。还公开了用于制造本发明的不同实施例的方法和过程。

2. 发明授权

US07125785B2 Mixed orientation and mixed material semiconductor-on-insulator wafer 有权
标题翻译：混合取向和混合材料绝缘体上半导体晶片
公开(公告)号：US07125785B2
公开(公告)日：2006-10-24
申请号：US10865920
申请日：2004-06-14
申请人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
发明人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
IPC分类号： H01L21/20
CPC分类号： H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.
摘要翻译：本公开通常涉及具有包括混合单晶取向区域和/或混合单晶半导体材料区域的平坦化表面的半导体衬底，其中每个区域是电隔离的。根据本公开的一个实施例，SOI区域上的CMOS器件在具有不同取向的半导体上制造。根据另一实施例，SOI器件被认为具有多个具有不同半导体材料，晶格常数或晶格应变中的至少一个的半导体区域。还公开了用于制造本发明的不同实施例的方法和过程。

3. 发明授权

US07449767B2 Mixed orientation and mixed material semiconductor-on-insulator wafer 有权
标题翻译：混合取向和混合材料绝缘体上半导体晶片
公开(公告)号：US07449767B2
公开(公告)日：2008-11-11
申请号：US11522905
申请日：2006-09-19
申请人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
发明人： Guy M. Cohen , Alexander Reznicek , Katherine L. Saenger , Min Yang
IPC分类号： H01L29/04
CPC分类号： H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.
摘要翻译：本公开通常涉及具有包括混合单晶取向区域和/或混合单晶半导体材料区域的平坦化表面的半导体衬底，其中每个区域是电隔离的。根据本公开的一个实施例，SOI区域上的CMOS器件在具有不同取向的半导体上制造。根据另一实施例，SOI器件被认为具有多个具有不同半导体材料，晶格常数或晶格应变中的至少一个的半导体区域。还公开了用于制造本发明的不同实施例的方法和过程。

4. 发明授权

US08241970B2 CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins 有权
标题翻译：具有沟道P-FinFET和沟道N-FinFET的CMOS具有不同的晶体取向和平行鳍片
公开(公告)号：US08241970B2
公开(公告)日：2012-08-14
申请号：US12197459
申请日：2008-08-25
申请人： Guy M. Cohen , Katherine L. Saenger
发明人： Guy M. Cohen , Katherine L. Saenger
IPC分类号： H01L21/00
CPC分类号： H01L27/0924 , H01L21/34 , H01L21/845 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785
摘要： An integrated circuit is fabricated with at least one p-FinFET device and at least one n-FinFET device situated parallel to each other. A first silicon layer having a first crystalline orientation is bonded to a second silicon layer having a second crystalline orientation. The first and second orientations are different from each other. A volume of material is formed that extends through the first layer from the second layer up to the surface of the first layer. The material has a crystalline orientation that substantially matches the orientation of the second layer. Areas of the surface of the first layer that are outside of the region are selectively etched to create a first plurality of fins and areas inside the region to create a second plurality of fins. The etching leaves the first and second pluralities of fins parallel to each other with different surface crystal orientations.
摘要翻译：制造具有至少一个p-FinFET器件和至少一个彼此平行的n-FinFET器件的集成电路。具有第一晶体取向的第一硅层被结合到具有第二晶体取向的第二硅层上。第一和第二取向彼此不同。形成一定体积的材料，其从第二层延伸穿过第一层直到第一层的表面。该材料具有基本上与第二层的取向一致的晶体取向。选择性地蚀刻在区域外部的第一层的表面的区域，以在该区域内产生第一多个散热片和区域，以产生第二多个散热片。蚀刻使得第一和第二多个翅片彼此平行但具有不同的表面晶体取向。

5. 发明授权

US08574969B2 CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins 失效
标题翻译：具有沟道P-FinFET和沟道N-FinFET的CMOS具有不同的晶体取向和平行鳍片
公开(公告)号：US08574969B2
公开(公告)日：2013-11-05
申请号：US13560322
申请日：2012-07-27
申请人： Guy M. Cohen , Katherine L. Saenger
发明人： Guy M. Cohen , Katherine L. Saenger
IPC分类号： H01L21/00
CPC分类号： H01L27/0924 , H01L21/34 , H01L21/845 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785
摘要： An integrated circuit fabrication apparatus is configured to fabricate an integrated circuit with at least one p-FinFET device and at least one n-FinFET device. A bonding control processor is configured to bond a first silicon layer having a first crystalline orientation to a second silicon layer having a second crystalline orientation that is different from the first crystalline orientation. A material growth processor is configured to form a volume of material extending through the first silicon layer from the second layer up to the surface of first layer. The material has a crystalline orientation that substantially matches the crystalline orientation of second layer. An etching processor is configured to selectively etch areas of the surface of the first layer that are outside of the region to create a first plurality of fins and areas inside the region to create a second plurality of fins.
摘要翻译：集成电路制造装置被配置为制造具有至少一个p-FinFET器件和至少一个n-FinFET器件的集成电路。键合控制处理器被配置为将具有第一晶体取向的第一硅层与具有不同于第一晶体取向的第二晶体取向的第二硅层结合。材料生长处理器被配置为形成从第二层延伸穿过第一硅层到第一层的表面的材料体积。该材料具有基本上与第二层的晶体取向一致的结晶取向。蚀刻处理器被配置为选择性地蚀刻位于该区域外部的第一层的表面的区域，以在该区域内形成第一多个散热片和区域，以产生第二多个翅片。

6. 发明授权

US08563369B2 CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins 有权
标题翻译：具有沟道P-FinFET和沟道N-FinFET的CMOS具有不同的晶体取向和平行鳍片
公开(公告)号：US08563369B2
公开(公告)日：2013-10-22
申请号：US13560340
申请日：2012-07-27
申请人： Guy M. Cohen , Katherine L. Saenger
发明人： Guy M. Cohen , Katherine L. Saenger
IPC分类号： H01L21/00
CPC分类号： H01L27/0924 , H01L21/34 , H01L21/845 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785
摘要： A method for fabricating an integrated circuit with at least one p-FinFET device and at least one n-FinFET device. The method includes bonding a first silicon layer having a first crystalline orientation to a second silicon layer having a second crystalline orientation that is different from the first crystalline orientation. A first plurality of fins and a second plurality of fins are created. A spacer is formed around each fin in the first plurality of fins and second plurality of fins. A set of regions of the second layer between each fin in the first plurality of fins and the second plurality of fins are recessed to form a base with exposed sidewalls under each fin in the first plurality of fins and the second plurality of fins. The base under each fin and a set of exposed regions between each fin is oxidized.
摘要翻译：一种用至少一个p-FinFET器件和至少一个n-FinFET器件制造集成电路的方法。该方法包括将具有第一晶体取向的第一硅层与具有不同于第一晶体取向的第二晶体取向的第二硅层结合。产生第一多个翅片和第二多个翅片。在第一多个翅片和第二多个翅片中的每个翅片周围形成间隔件。在第一多个翅片中的每个翅片和第二多个翅片之间的第二层的一组区域被凹入以在第一多个翅片和第二多个翅片中的每个翅片下方形成具有暴露的侧壁的底部。每个翅片下面的基底和每个翅片之间的一组暴露区域被氧化。

7. 发明授权

US07315065B2 Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates 有权
标题翻译：用于制造绝缘体上硅（SGOI）和绝缘体上（GeI）绝缘体（GOI）基板的方法
公开(公告)号：US07315065B2
公开(公告)日：2008-01-01
申请号：US11481525
申请日：2006-07-06
申请人： Tze-chiang Chen , Guy M. Cohen , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Tze-chiang Chen , Guy M. Cohen , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L29/12 , H01L31/036 , H01L71/01 , H01L71/12 , H01L31/309
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

8. 发明授权

US07498235B2 Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates 有权
标题翻译：用于制造绝缘体上硅（SGOI）和绝缘体上（GeI）绝缘体（GOI）基板的方法
公开(公告)号：US07498235B2
公开(公告)日：2009-03-03
申请号：US11924207
申请日：2007-10-25
申请人： Tze-chiang Chen , Guy M. Cohen , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Tze-chiang Chen , Guy M. Cohen , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

9. 发明授权

US07084460B2 Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates 有权
公开(公告)号：US07084460B2
公开(公告)日：2006-08-01
申请号：US10700085
申请日：2003-11-03
申请人： Tze-chiang Chen , Guy M. Cohen , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Tze-chiang Chen , Guy M. Cohen , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L29/12 , H01L31/036 , H01L71/01 , H01L71/12 , H01L31/039
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

10. 发明授权

US06946696B2 Self-aligned isolation double-gate FET 有权
标题翻译：自对准隔离双栅极FET
公开(公告)号：US06946696B2
公开(公告)日：2005-09-20
申请号：US10328285
申请日：2002-12-23
申请人： Kevin K. Chan , Guy M. Cohen , Meikei Ieong , Ronnen A. Roy , Paul Solomon , Min Yang
发明人： Kevin K. Chan , Guy M. Cohen , Meikei Ieong , Ronnen A. Roy , Paul Solomon , Min Yang
IPC分类号： H01L29/417 , H01L21/02 , H01L21/265 , H01L21/336 , H01L21/76 , H01L21/762 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786 , H01C27/148
CPC分类号： H01L29/66484 , H01L21/26533 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66772 , H01L29/7831 , H01L29/7834 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。提供了两种降低源极/漏极区下寄生电容的新手段。首先，栅极外部的硅区域被转换为氧化物，同时用第一间隔物保护邻近栅极的硅凸缘。使用自对准氧植入物或某些其它物种的植入物可以促进氧化。其次，去除第一间隔物，用第二间隔物代替，通过采用横向选择性外延生长并使用现在暴露的硅壁缘作为种子，在自对准氧化物隔离区域上生长新的硅源/漏区。这实现了对背板的低电容，同时保持阈值电压的控制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式