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1. 发明授权

US09337026B2 Graphene growth on a carbon-containing semiconductor layer 有权
标题翻译：含碳半导体层上的石墨烯生长
公开(公告)号：US09337026B2
公开(公告)日：2016-05-10
申请号：US13443003
申请日：2012-04-10
申请人： Jack O. Chu , Christos D. Dimitrakopoulos , Alfred Grill , Chun-yung Sung
发明人： Jack O. Chu , Christos D. Dimitrakopoulos , Alfred Grill , Chun-yung Sung
IPC分类号： H01L21/02 , B82Y30/00 , B82Y40/00 , C01B31/04
CPC分类号： H01L29/1606 , B82Y30/00 , B82Y40/00 , C01B32/184 , C01B2204/04 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02527 , H01L21/0262 , H01L21/02664 , H01L21/02667 , H01L29/045 , H01L29/1608 , H01L29/161 , Y10T428/265
摘要： A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.
摘要翻译：半导体 - 碳合金层形成在半导体衬底的表面上，半导体衬底的表面可以是诸如硅衬底的市售半导体衬底。半导体 - 碳合金层在高温退火期间被转化为至少一个石墨烯层，在此期间半导体 - 碳合金层表面上的半导体材料对碳原子有选择性的蒸发。随着半导体原子被选择性地去除并且半导体 - 碳合金层的表面上的碳浓度增加，半导体 - 碳合金层顶层中剩余的碳原子聚结形成具有至少一个石墨烯单层的石墨烯层。因此，可以在直径为200mm或300mm的市售半导体衬底上提供石墨烯层。

2. 发明授权

US08405127B2 Method and apparatus for fabricating a heterojunction bipolar transistor 有权
标题翻译：用于制造异质结双极晶体管的方法和装置
公开(公告)号：US08405127B2
公开(公告)日：2013-03-26
申请号：US12034210
申请日：2008-02-20
申请人： Jack O. Chu , Francois Pagette
发明人： Jack O. Chu , Francois Pagette
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L29/45 , H01L29/66242
摘要： In one embodiment, the invention is a method and apparatus for fabricating a heterojunction bipolar transistor. One embodiment of a heterojunction bipolar transistor includes a collector layer, a base region formed over the collector layer, a self-aligned emitter formed on top of the base region and collector layer, a poly-germanium extrinsic base surrounding the emitter, and a metal germanide layer formed over the extrinsic base.
摘要翻译：在一个实施例中，本发明是用于制造异质结双极晶体管的方法和装置。异质结双极晶体管的一个实施例包括集电极层，形成在集电极层上的基极区域，形成在基极区域和集电极层顶部的自对准发射极，围绕发射极的聚锗外基极和金属形成在外在基础上的锗化物层。

3. 发明申请

US20120319078A1 GRAPHENE GROWTH ON A NON-HEXAGONAL LATTICE 审中-公开
标题翻译：非黑龙江地区的石墨生长
公开(公告)号：US20120319078A1
公开(公告)日：2012-12-20
申请号：US13596152
申请日：2012-08-28
申请人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
发明人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
IPC分类号： H01L29/06 , B82Y99/00
CPC分类号： H01L21/02527 , B82Y30/00 , B82Y40/00 , C01B32/188 , H01L21/02378 , H01L21/02433 , H01L21/02447 , H01L21/02516 , Y10T428/30
摘要： A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.
摘要翻译：在具有非六边形对称性的结晶表面上形成石墨烯层。晶体表面可以是单晶半导体碳化物层的表面。单晶半导体碳化物层的非六边形对称表面在超高真空环境中在升高的温度下退火以形成石墨烯层。在退火过程中，单晶半导体碳化物层的非六边形表面上的半导体原子对碳原子有选择性的蒸发。随着半导体原子被选择性地去除，半导体 - 碳合金层表面上的碳浓度增加。尽管半导体 - 碳合金层的表面具有非六边形对称性，但剩余的碳原子可以聚结形成具有六边形对称性的石墨烯层。

4. 发明授权

US08178382B2 Suspended germanium photodetector for silicon waveguide 有权
标题翻译：用于硅波导的悬浮锗光电探测器
公开(公告)号：US08178382B2
公开(公告)日：2012-05-15
申请号：US13005821
申请日：2011-01-13
申请人： Solomon Assefa , Jack O. Chu , Martin M. Frank , William M. Green , Young-hee Kim , George G. Totir , Joris Van Campenhout , Yurri A. Vlasov , Ying Zhang
发明人： Solomon Assefa , Jack O. Chu , Martin M. Frank , William M. Green , Young-hee Kim , George G. Totir , Joris Van Campenhout , Yurri A. Vlasov , Ying Zhang
IPC分类号： H01L31/18
CPC分类号： H01L31/1804 , B82Y20/00 , G02B6/12004 , G02B6/136 , G02B2006/12123 , H01L31/109 , H01L31/1812 , Y02E10/547 , Y02P70/521
摘要： A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.
摘要翻译：在第一外延硅层的顶表面上外延地形成第一硅锗合金层，第二外延硅层，第二硅锗层和锗层的垂直叠层。第二外延硅层，第二硅锗层和锗层通过介电盖部分，电介质间隔物和第一硅锗层被图案化和封装。在第一和第二硅层之间去除硅锗层以形成硅锗台面结构，其结构上支撑包括硅部分，硅锗合金部分，锗光电检测器和介电帽部分的叠层的悬垂结构。锗光电探测器由硅锗台面结构悬挂而不邻接硅波导。锗扩散到硅波导和锗检测器中的缺陷密度被最小化。

5. 发明申请

US20110206934A1 GRAPHENE FORMATION UTILIZING SOLID PHASE CARBON SOURCES 有权
标题翻译：利用固相碳源的石墨形成
公开(公告)号：US20110206934A1
公开(公告)日：2011-08-25
申请号：US12710333
申请日：2010-02-22
申请人： Ageeth A. Bol , Roy A. Carruthers , Jack O. Chu , Alfred Grill , Christian Lavoie , Katherine L. Saenger , James C. Tsang
发明人： Ageeth A. Bol , Roy A. Carruthers , Jack O. Chu , Alfred Grill , Christian Lavoie , Katherine L. Saenger , James C. Tsang
IPC分类号： B32B9/00 , B32B15/04 , B05D3/02
CPC分类号： C01B31/0446 , B82Y30/00 , B82Y40/00 , C01B32/184 , Y10T428/30
摘要： A method for forming a single, few-layer, or multi-layer graphene and structure is described incorporating selecting a substrate having a buried layer of carbon underneath a metal layer, providing an ambient and providing a heat treatment to pass carbon through the metal layer to form a graphene layer on the metal layer surface or incorporating a metal-carbon layer which is heated to segregate carbon in the form of graphene to the surface or chemically reacting the metal in the metal-carbon layer with a substrate containing Si driving the carbon to the surface whereby graphene is formed.
摘要翻译：描述了形成单层，几层或多层石墨烯和结构的方法，其包括选择在金属层下方具有埋藏层的衬底的基底，提供环境并提供热处理以使碳通过金属层以在金属层表面上形成石墨烯层或掺入金属碳层，该金属碳层被加热以将石墨烯形式的碳分离到表面或使金属 - 碳层中的金属与含有驱动碳的Si的基板化学反应到形成石墨烯的表面。

6. 发明授权

US07786468B2 Layer transfer of low defect SiGe using an etch-back process 失效
标题翻译：使用回蚀工艺对低缺陷SiGe进行层传输
公开(公告)号：US07786468B2
公开(公告)日：2010-08-31
申请号：US12181613
申请日：2008-07-29
申请人： Jack O. Chu , David R. DiMilia , Lijuan Huang
发明人： Jack O. Chu , David R. DiMilia , Lijuan Huang
IPC分类号： H01L29/737
CPC分类号： H01L21/76256 , H01L21/2007
摘要： A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.
摘要翻译：描述了在半导体衬底上增长的外延Si1-yGey层，通过Chemo-Mechanical Polishing平滑表面，通过热粘合将两个衬底粘合在一起，在绝缘体上松弛的SiGe（SiO）或Si异质结构上的SiGe上形成应变Si或SiGe的方法处理并通过使用SiGe本身作为蚀刻停止的高选择性蚀刻将SiGe层从一个衬底转移到另一个衬底。转移的SiGe层可以通过CMP平滑CMP，用于外延沉积弛豫Si1-yGey，并且应变Si1-yGey取决于组成，应变Si，应变SiC，应变Ge，应变GeC和应变Si1-yGeyC或重度掺杂层以形成SiGe / Si异质结二极管的电接触。

7. 发明申请

US20090206413A1 CMOS INTEGRATION SCHEME EMPLOYING A SILICIDE ELECTRODE AND A SILICIDE-GERMANIDE ALLOY ELECTRODE 失效
标题翻译：使用硅酮电极和硅锗合金电极的CMOS集成方案
公开(公告)号：US20090206413A1
公开(公告)日：2009-08-20
申请号：US12031224
申请日：2008-02-14
申请人： Cyril Cabral, JR. , Jack O. Chu , Young-Hee Kim
发明人： Cyril Cabral, JR. , Jack O. Chu , Young-Hee Kim
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823835 , H01L21/28052 , H01L21/28518 , H01L21/823842 , H01L21/82385 , H01L29/4933 , H01L29/517 , H01L29/665 , H01L29/66545 , Y10S438/933
摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon-germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon germanium alloy portions are removed from gate stacks. A dielectric layer is formed and patterned to cover an NFET gate electrode, while exposing a thin silicon portion for a PFET. Germanium is selectively deposited on semiconductor surfaces including the exposed silicon portion. The dielectric layer is removed and a metal layer is deposited and reacted with underlying semiconductor material to form a metal silicide for a gate electrode of the NFET, while forming a metal silicide-germanide alloy for a gate electrode of the PFET.
摘要翻译：通过构图栅极电介质层，薄硅层和硅 - 锗合金层来形成p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。在形成源极/漏极区域和栅极间隔物之后，从栅极叠层去除硅锗合金部分。形成介电层并图案化以覆盖NFET栅电极，同时暴露用于PFET的薄硅部分。锗选择性地沉积在包括暴露的硅部分的半导体表面上。去除电介质层，并沉积金属层并与下面的半导体材料反应以形成用于NFET的栅电极的金属硅化物，同时形成用于PFET的栅电极的金属硅化物 - 锗化物合金。

8. 发明申请

US20090004831A1 METHOD OF CREATING DEFECT FREE HIGH Ge CONTENT (> 25%) SiGe-ON-INSULATOR (SGOI) SUBSTRATES USING WAFER BONDING TECHNIQUES 有权
标题翻译：使用波形焊接技术创建无缺陷高锗含量（> 25％）SiGe-ON-INSULATOR（SGOI）基板的方法
公开(公告)号：US20090004831A1
公开(公告)日：2009-01-01
申请号：US12140600
申请日：2008-06-17
申请人： Jack O. Chu , Michael A. Cobb , Philip A. Saunders , Leathen Shi
发明人： Jack O. Chu , Michael A. Cobb , Philip A. Saunders , Leathen Shi
IPC分类号： H01L21/20
CPC分类号： H01L21/76254 , H01L21/0245 , H01L21/0251 , H01L29/1054
摘要： A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.
摘要翻译：描述了使用低温晶片接合技术来实现包括具有大于约25原子％的高Ge含量的SiGe层的基本上无缺陷的SGOI衬底的方法。本申请中描述的晶片接合方法包括初始预结合退火步骤，其能够形成包含SiGe层和低温氧化物层之间的Si，Ge和O元素即界面SiGeO层的键合界面。本发明还提供了包含其的SGOI衬底和结构。

9. 发明授权

US07445977B2 Method of creating defect free high Ge content (> 25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques 失效
标题翻译：使用晶片接合技术产生无缺陷的高Ge含量（> 25％）绝缘体上硅（SGOI）衬底的方法
公开(公告)号：US07445977B2
公开(公告)日：2008-11-04
申请号：US11744600
申请日：2007-05-04
申请人： Jack O. Chu , Michael A. Cobb , Philip A. Saunders , Leathen Shi
发明人： Jack O. Chu , Michael A. Cobb , Philip A. Saunders , Leathen Shi
IPC分类号： H01L21/336
CPC分类号： H01L21/76254 , H01L21/0245 , H01L21/0251 , H01L29/1054
摘要： A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.
摘要翻译：描述了使用低温晶片接合技术来实现包括具有大于约25原子％的高Ge含量的SiGe层的基本上无缺陷的SGOI衬底的方法。本申请中描述的晶片接合方法包括初始预结合退火步骤，其能够形成包含SiGe层和低温氧化物层之间的Si，Ge和O元素即界面SiGeO层的键合界面。本发明还提供了包含其的SGOI衬底和结构。

10. 发明申请

US20080185618A1 STRUCTURE FOR AND METHOD OF FABRICATING A HIGH-SPEED CMOS-COMPATIBLE Ge-ON-INSULATOR PHOTODETECTOR 有权
标题翻译：高速CMOS兼容Ge-ON-INSULATOR光电转换器的结构和方法
公开(公告)号：US20080185618A1
公开(公告)日：2008-08-07
申请号：US11556755
申请日：2006-11-06
申请人： Jack O. Chu , Gabriel K. Dehlinger , Alfred Grill , Steven J. Koester , Qiqing Ouyang , Jeremy D. Schaub
发明人： Jack O. Chu , Gabriel K. Dehlinger , Alfred Grill , Steven J. Koester , Qiqing Ouyang , Jeremy D. Schaub
IPC分类号： H01L27/146
CPC分类号： H01L31/101
摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.
摘要翻译：本发明解决了与Si CMOS技术兼容的高速高效光电探测器的问题。该结构由薄的SOI衬底上的Ge吸收层组成，并且使用隔离区，交替的n型和p型接触以及低电阻表面电极。该器件通过利用掩埋绝缘层来隔离衬底中产生的载流子，通过利用Ge吸收层，在广谱上产生高量子效率，利用薄吸收层和窄电极间隔的低电压操作以及兼容性来实现高带宽通过其平面结构和使用IV族吸收材料的CMOS器件。用于制造光电检测器的方法使用在薄SOI或外延氧化物上的Ge的直接生长，以及随后的热退火以实现高质量的吸收层。该方法限制可用于相互扩散的Si的量，从而允许Ge层退火，而不会导致Ge层被下面的Si大量稀释。

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