专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06759710B2 Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques 失效
标题翻译：通过选择性外延和硅晶片结合技术的自对准双栅极MOSFET
公开(公告)号：US06759710B2
公开(公告)日：2004-07-06
申请号：US10051562
申请日：2002-01-18
申请人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
发明人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
IPC分类号： H01L2976
CPC分类号： H01L29/78654 , H01L21/76251 , H01L21/76264 , H01L21/76275 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/78648 , H01L29/78684 , H01L29/78687 , H01L29/78696
摘要： A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.
摘要翻译：制造双栅极金属氧化物半导体晶体管的结构和方法包括在单晶硅沟道的每一侧上形成具有单晶硅沟道层和绝缘氧化物层和氮化物层的叠层结构，在层叠结构中形成开口，在开口中形成漏极和源极区域，掺杂漏极和源极区域，在层压结构上形成掩模，去除未被掩模保护的层压结构的部分，去除掩模和绝缘氧化物和氮化物层以留下单个从漏极和源极区域悬置的晶体硅沟道层，形成覆盖漏极和源极区域和沟道层的氧化物层，以及在氧化物层上形成双栅极导体，使得双栅极导体包括第一导体在单晶硅沟道层的第一侧和在单晶的第二面上的第二导体 l硅通道层。

2. 发明授权

US06365465B1 Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques 失效
标题翻译：通过选择性外延和硅晶片结合技术的自对准双栅极MOSFET
公开(公告)号：US06365465B1
公开(公告)日：2002-04-02
申请号：US09272297
申请日：1999-03-19
申请人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
发明人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
IPC分类号： H01L21336
CPC分类号： H01L29/78654 , H01L21/76251 , H01L21/76264 , H01L21/76275 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/78648 , H01L29/78684 , H01L29/78687 , H01L29/78696
摘要： A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.
摘要翻译：制造双栅极金属氧化物半导体晶体管的结构和方法包括在单晶硅沟道的每一侧上形成具有单晶硅沟道层和绝缘氧化物层和氮化物层的叠层结构，在层叠结构中形成开口，在开口中形成漏极和源极区域，掺杂漏极和源极区域，在层压结构上形成掩模，去除未被掩模保护的层压结构的部分，去除掩模和绝缘氧化物和氮化物层以留下单个从漏极和源极区域悬置的晶体硅沟道层，形成覆盖漏极和源极区域和沟道层的氧化物层，以及在氧化物层上形成双栅极导体，使得双栅极导体包括第一导体在单晶硅沟道层的第一侧和在单晶的第二面上的第二导体 l硅通道层。

3. 发明授权

US5604368A Self-aligned double-gate MOSFET by selective lateral epitaxy 失效
标题翻译：通过选择性横向外延自对准双栅极MOSFET
公开(公告)号：US5604368A
公开(公告)日：1997-02-18
申请号：US407175
申请日：1995-03-21
申请人： Yuan Taur , Hon-Sum P. Wong
发明人： Yuan Taur , Hon-Sum P. Wong
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786 , H01L27/01 , H01L27/12 , H01L29/76
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A novel method of fabricating a double-gate MOSFET structure is disclosed. The method utilizes selective lateral epitaxial growth of silicon into a thin gap formed between two sacrificial dielectric films for accurate thickness control. The sacrificial films are then replaced by a gate material (e.g., polysilicon) such that top and bottom gates are self-aligned to each other and to the channel region. Also disclosed is a self-aligned double-gate MOSFET constructed in accordance with the foregoing method.
摘要翻译：公开了一种制造双栅极MOSFET结构的新方法。该方法利用硅的选择性横向外延生长成形成在两个牺牲绝缘膜之间的薄间隙，用于精确的厚度控制。牺牲膜然后由栅极材料（例如，多晶硅）代替，使得顶部栅极和底部栅极彼此自对准并且与沟道区域相对。还公开了根据前述方法构造的自对准双栅极MOSFET。

4. 发明授权

US06982460B1 Self-aligned gate MOSFET with separate gates 有权
标题翻译：具有分离栅极的自对准栅极MOSFET
公开(公告)号：US06982460B1
公开(公告)日：2006-01-03
申请号：US09612260
申请日：2000-07-07
申请人： Guy M. Cohen , Hon-Sum P. Wong
发明人： Guy M. Cohen , Hon-Sum P. Wong
IPC分类号： H01L29/76 , H01L27/01
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A structure and method of manufacturing a double-gate integrated circuit which includes forming a laminated structure having a channel layer and first insulating layers on each side of the channel layer, forming openings in the laminated structure, forming drain and source regions in the openings, removing portions of the laminated structure to leave a first portion of the channel layer exposed, forming a first gate dielectric layer on the channel layer, forming a first gate electrode on the first gate dielectric layer, removing portions of the laminated structure to leave a second portion of the channel layer exposed, forming a second gate dielectric layer on the channel layer, forming a second gate electrode on the second gate dielectric layer, doping the drain and source regions, using self-aligned ion implantation, wherein the first gate electrode and the second gate electrode are formed independent of each other.
摘要翻译：一种制造双栅极集成电路的结构和方法，包括在沟道层的每一侧上形成具有沟道层和第一绝缘层的层叠结构，在层叠结构中形成开口，在开口中形成漏极和源极区域，去除所述层叠结构的部分以使所述沟道层的第一部分暴露，在所述沟道层上形成第一栅极电介质层，在所述第一栅极介电层上形成第一栅电极，去除所述层叠结构的部分以留下第二栅极电介质层在所述沟道层上形成第二栅极电介质层，在所述第二栅极电介质层上形成第二栅极电极，使用自对准离子注入来掺杂所述漏极和源极区域，其中所述第一栅电极和第二栅电极彼此独立地形成。

5. 发明授权

US06967377B2 Double-gate fet with planarized surfaces and self-aligned silicides 失效
标题翻译：具有平面化表面和自对准硅化物的双栅极fet
公开(公告)号：US06967377B2
公开(公告)日：2005-11-22
申请号：US10629014
申请日：2003-07-29
申请人： Guy M. Cohen , Hon-Sum P. Wong
发明人： Guy M. Cohen , Hon-Sum P. Wong
IPC分类号： H01L21/336 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L29/78696 , H01L27/1203 , H01L29/66772 , H01L29/78618 , H01L29/78648
摘要： It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit comprising a first gate, a second gate, and source and drain regions adjacent the first and second gates, wherein the structure has a planar upper structure and the first gate, source and drain regions are silicided in a single self-aligned process (salicide).
摘要翻译：因此，本发明的目的是提供一种用于集成电路的结构和方法，该集成电路包括第一栅极，第二栅极以及与第一和第二栅极相邻的源极和漏极区域，其中该结构具有平面上部结构并且第一栅极，源极和漏极区域在单个自对准过程（硅化物）中被硅化。

6. 发明授权

US06642115B1 Double-gate FET with planarized surfaces and self-aligned silicides 失效
标题翻译：具有平面化表面和自对准硅化物的双栅极FET
公开(公告)号：US06642115B1
公开(公告)日：2003-11-04
申请号：US09690875
申请日：2000-10-18
申请人： Guy M. Cohen , Hon-Sum P. Wong
发明人： Guy M. Cohen , Hon-Sum P. Wong
IPC分类号： H01L2100
CPC分类号： H01L29/78696 , H01L27/1203 , H01L29/66772 , H01L29/78618 , H01L29/78648
摘要： It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit comprising a first gate, a second gate, and source and drain regions adjacent the first and second gates, wherein the structure has a planar upper structure and the first gate, source and drain regions are silicided in a single self-aligned process (salicide).
摘要翻译：因此，本发明的目的是提供一种用于集成电路的结构和方法，该集成电路包括与第一和第二栅极相邻的第一栅极，第二栅极和源极和漏极区域，其中该结构具有平面上部结构并且第一栅极，源极和漏极区域在单个自对准过程（硅化物）中被硅化。

7. 发明授权

US07101762B2 Self-aligned double gate mosfet with separate gates 失效
标题翻译：自对准双门mosfet与分离的门
公开(公告)号：US07101762B2
公开(公告)日：2006-09-05
申请号：US11050366
申请日：2005-02-03
申请人： Guy M. Cohen , Hon-Sum P. Wong
发明人： Guy M. Cohen , Hon-Sum P. Wong
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A structure and method of manufacturing a double-gate integrated circuit which includes forming a laminated structure having a channel layer and first insulating layers on each side of the channel layer, forming openings in the laminated structure, forming drain and source regions in the openings, removing portions of the laminated structure to leave a first portion of the channel layer exposed, forming a first gate dielectric layer on the channel layer, forming a first gate electrode on the first gate dielectric layer, removing portions of the laminated structure to leave a second portion of the channel layer exposed, forming a second gate dielectric layer on the channel layer, forming a second gate electrode on the second gate dielectric layer, doping the drain and source regions, using self-aligned ion implantation, wherein the first gate electrode and the second gate electrode are formed independent of each other.
摘要翻译：一种制造双栅极集成电路的结构和方法，包括在沟道层的每一侧上形成具有沟道层和第一绝缘层的层叠结构，在层叠结构中形成开口，在开口中形成漏极和源极区域，去除所述层叠结构的部分以使所述沟道层的第一部分暴露，在所述沟道层上形成第一栅极电介质层，在所述第一栅极介电层上形成第一栅电极，去除所述层叠结构的部分以留下第二栅极电介质层在所述沟道层上形成第二栅极电介质层，在所述第二栅极电介质层上形成第二栅极电极，使用自对准离子注入来掺杂所述漏极和源极区域，其中所述第一栅电极和第二栅电极彼此独立地形成。

8. 发明授权

US07057923B2 Field emission phase change diode memory 失效
标题翻译：场发射相变二极管存储器
公开(公告)号：US07057923B2
公开(公告)日：2006-06-06
申请号：US10732582
申请日：2003-12-10
申请人： Stephen S. Furkay , David V. Horak , Chung H. Lam , Hon-Sum P. Wong
发明人： Stephen S. Furkay , David V. Horak , Chung H. Lam , Hon-Sum P. Wong
IPC分类号： G11C11/00 , H01L27/00 , H01L21/00
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： A storage cell that may be a memory cell, and integrated circuit (IC) chip including an array of the memory cells and a method of forming the IC. Each storage cell is formed between a top an bottom electrode. Each cell includes a phase change layer that may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) or GST layer. The cell also includes a stylus with the apex of the stylus contacting the GST layer. The apex may penetrate the GST layer
摘要翻译：可以是存储单元的存储单元和包括存储单元的阵列的集成电路（IC）芯片和形成IC的方法。每个存储单元形成在顶部底部电极之间。每个电池包括可以是硫族化物，特别是锗（Ge），锑（Sb），碲（Te）或GST层的相变层。电池还包括一个触笔，触笔的顶点与GST层接触。顶点可以穿透GST层

9. 发明授权

US5334868A Sidewall charge-coupled device with trench isolation 失效
标题翻译：侧壁电荷耦合器件具有沟槽隔离
公开(公告)号：US5334868A
公开(公告)日：1994-08-02
申请号：US57425
申请日：1993-05-05
申请人： Hon-Sum P. Wong
发明人： Hon-Sum P. Wong
IPC分类号： H01L21/763 , H01L27/148 , H01L29/78 , H01L27/14 , H01L31/00
CPC分类号： H01L27/14856 , H01L21/763 , H01L27/14812 , H01L27/14831
摘要： A charge-coupled imaging device comprising a plurality of trenches in the surface of the silicon substrate which separate adjacent columns in the CCD device. A plurality of surface electrodes are provided on the surface of the charge-coupled device extending perpendicular to the isolation trenches, which electrodes provide for clocked transfer of charges between adjacent cells within each column of the charge-coupled device. The CCD cells are formed on the silicon ridges delineated between the isolation trenches, and this structure maximizes the three dimensional surface area of the CCD cells and facilitates transport of charges along the CCD cell sidewalls. The sidewall CCD with trench isolation provides a CCD cell layout size the same as that of a conventional two dimensional CCD cell, but with an increased charge capacity per CCD cell because of the larger three dimensional areas of the CCD cells. The increase in charge capacity means a larger signal-to-noise ratio and consequently a larger dynamic range. In one embodiment, a plurality of shallow electrodes are defined under the surface electrodes to increase the charge carrying surface area and provide better gate control.
摘要翻译：一种电荷耦合成像装置，其在所述硅基板的表面中包括在所述CCD器件中分离相邻列的多个沟槽。多个表面电极设置在垂直于隔离沟槽延伸的电荷耦合器件的表面上，这些电极提供电荷耦合器件的每列内的相邻单元之间的电荷时钟传输。 CCD单元形成在描绘在隔离沟槽之间的硅脊上，并且该结构使CCD单元的三维表面积最大化并且有助于电荷沿着CCD单元侧壁的传输。具有沟槽隔离的侧壁CCD提供与常规二维CCD单元相同的CCD单元布局尺寸，但是由于CCD单元的较大的三维区域，每个CCD单元具有增加的电荷容量。充电容量的增加意味着较大的信噪比，因此具有较大的动态范围。在一个实施例中，多个浅电极被限定在表面电极下面，以增加电荷承载表面积并提供更好的栅极控制。

10. 发明授权

US5173756A Trench charge-coupled device 失效
标题翻译：沟槽电荷耦合器件
公开(公告)号：US5173756A
公开(公告)日：1992-12-22
申请号：US698361
申请日：1991-05-08
申请人： Hon-Sum P. Wong , Ying L. Yao
发明人： Hon-Sum P. Wong , Ying L. Yao
IPC分类号： H01L27/148
CPC分类号： H01L27/14831
摘要： A charge-coupled device having a three-dimensional trench structure that achieves a highly effective sensing and storage area in a CCD imager while maintaining a small cell layout area. The trench CCD device includes a plurality of trench electrodes etched in the surface of the device, with surface electrodes in between. The trenches are shaped to facilitate charge transfer along their sidewalls and to maximize trench surface area.
摘要翻译：一种具有三维沟槽结构的电荷耦合器件，其在CCD成像器中实现高度有效的感测和存储区域，同时保持小的单元布局区域。沟槽CCD器件包括在器件的表面中蚀刻的多个沟槽电极，其间具有表面电极。沟槽被成形为便于沿其侧壁的电荷转移并且最大化沟槽表面积。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式