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21. 发明授权

US6073182A Method of resolving deadlocks between competing requests in a multiprocessor using global hang pulse logic 失效
标题翻译：使用全局挂起脉冲逻辑解决多处理器中竞争请求之间的死锁的方法
公开(公告)号：US6073182A
公开(公告)日：2000-06-06
申请号：US70664
申请日：1998-04-30
申请人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
发明人： Christine Comins Jones , Pak-kin Mak , Michael A. Blake , Michael Fee , Gary Eugene Strait
IPC分类号： G06F13/16 , G06F15/16 , G06F15/173
CPC分类号： G06F13/1663
摘要： A method using a global hang pulse logic mechanism detects and resolves deadlocks among requesters to the storage controller of a symmetric multiprocessor system in which multiple central processors and I/O adapters are connected to one or more shared storage controllers. Deadlocks may occur in such a system due to specific sequences of requests, either because high priority requests use priority cycles and lock out low priority requests, or because requests of any priority level make resources needed for the completion of other requests too busy. The mechanism logic monitors the length of time a request has been valid in the storage controller without completing, by checking the request register valid bits, and by utilizing a timed pulse which is a subset of the pulse used to detect hangs within the storage controller. If the valid bit is reset at any time detection logic and an internal hang detect latch is set, Logic which allows requests in progress to complete, and holds new requests in an inactive state is activated when the internal hang latch is set and remains active until the request which detected the internal hang is able to complete, thus resetting the internal hang detect latch.
摘要翻译：使用全局挂起脉冲逻辑机制的方法检测并解决请求者之间的死锁到其中多个中央处理器和I / O适配器连接到一个或多个共享存储控制器的对称多处理器系统的存储控制器。由于高优先级请求使用优先级周期并锁定低优先级请求，或者由于任何优先级的请求使得完成其他请求太繁忙所需的资源，因此在这种系统中可能会由于特定的请求序列而在这样的系统中发生死锁。机制逻辑监视存储控制器中的请求已经有效的时间长度，而不需要通过检查请求寄存器有效位以及利用作为用于检测存储控制器内的挂起的脉冲的子集的定时脉冲来完成。如果有效位在任何时候被复位，则检测逻辑和内部挂起检测锁存器被置位，当内部挂起锁存器被设置并且保持有效时，激活允许正在进行中的请求完成并保持处于非活动状态的新请求的逻辑，直到检测到内部挂起的请求能够完成，从而重置内部挂起检测锁存器。

22. 发明授权

US08918587B2 Multilevel cache hierarchy for finding a cache line on a remote node 有权
标题翻译：用于在远程节点上查找缓存行的多级缓存层次结构
公开(公告)号：US08918587B2
公开(公告)日：2014-12-23
申请号：US13495373
申请日：2012-06-13
申请人： Timothy C. Bronson , Garrett M. Drapala , Michael A. Blake , Craig R. Walters , Pak-Kin Mak
发明人： Timothy C. Bronson , Garrett M. Drapala , Michael A. Blake , Craig R. Walters , Pak-Kin Mak
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0884 , G06F12/123
摘要： Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.
摘要翻译：实施例涉及在具有系统存储器的多级缓存系统上访问高速缓存行。基于本地节点对特定高速缓存线的独占所有权的请求，请求被本地节点同时发送到用于特定高速缓存行的多个节点的系统内存和远程节点。在特定的远程节点中找到特定的高速缓存行。特定的远程节点是远程节点之一。从特定的远程节点中删除特定的高速缓存行以供另一个节点独占所有。基于具有指定缓存行在幽灵状态的指定节点，任何后续的提取请求将针对具体的缓存行启动，特定的缓存行遇到幽灵状态。当遇到鬼状态时，后续的提取请求仅被引导到多个节点的节点。

23. 发明授权

US08763979B2 Vehicle seat latch having striker compliance in transverse directions 失效
标题翻译：车辆座椅闩锁在横向上具有撞击顺从性
公开(公告)号：US08763979B2
公开(公告)日：2014-07-01
申请号：US13478480
申请日：2012-05-23
申请人： Michael A. Blake , Sobieslaw W. Derbis
发明人： Michael A. Blake , Sobieslaw W. Derbis
IPC分类号： B60N2/005
CPC分类号： B60N2/01583
摘要： The vehicle seat latch (16) disclosed includes an elongate pivot plate (32) pivotally mounted by a first pivotal connection (36) on a seat frame (28) by a mounting plate (26). A second pivotal connection (42) mounts a latch assembly (40) on the pivot plate (32). The latch assembly (40) includes a throat plate (46) having a throat (48) for receiving a vehicle body mounted striker (24), and the latch assembly (40) also includes at least one latch member (50, 52) movable between latched and unlatched positions for securing the latch to the striker (24). Pivoting of the pivot plate (32) about the first pivotal connection (36) and pivoting of the throat plate (46) about the second pivotal connection (42) provide the latch assembly with compliance that accommodates for striker position variation along transverse directions, which are vertical and horizontal when the seat is latched to the vehicle floor.
摘要翻译：所公开的车辆座椅闩锁（16）包括通过安装板（26）通过第一枢转连接（36）枢转地安装在座椅框架（28）上的细长枢转板（32）。第二枢转连接（42）将闩锁组件（40）安装在枢轴板（32）上。闩锁组件（40）包括具有用于接纳车身安装的撞击器（24）的喉部（48）的喉板（46），并且闩锁组件（40）还包括至少一个可移动的闩锁构件（50,52）在闩锁和解锁位置之间，用于将闩锁固定到撞针（24）。枢转板（32）围绕第一枢转连接件（36）枢转并且枢转板（46）围绕第二枢转连接件（42）枢转为闩锁组件提供符合性，以适应沿横向方向的撞击器位置变化，当座椅被闩锁到车辆地板时，它们是垂直和水平的。

24. 发明授权

US08364904B2 Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computer 失效
标题翻译：多计算节点，对称多处理计算机中的水平缓存持久性
公开(公告)号：US08364904B2
公开(公告)日：2013-01-29
申请号：US12819348
申请日：2010-06-21
申请人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski , Craig R. Walters
发明人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski , Craig R. Walters
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/084
摘要： Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.
摘要翻译：包括在多计算节点SMP计算机中的水平缓存持续性，包括响应于在计算节点的第一个计算节点上驱逐高速缓存行的确定，由第一计算节点广播高速缓存行的逐出通知; 发送接收计算节点的高速缓存行的状态，包括如果高速缓存线从计算节点丢失，则指示该计算节点是否具有可用于高速缓存行的高速缓存存储空间; 由所述第一计算节点根据所述高速缓存行的状态和可用空间来确定所述第一计算节点是否可以驱逐所述高速缓存行而不将高速缓存行写入主存储器; 并且根据所有计算节点中的高速缓存行的一个或多个状态，由每个计算节点更新每个计算节点中的高速缓存行的状态。

25. 发明申请

US20110320755A1 TRACKING DYNAMIC MEMORY REALLOCATION USING A SINGLE STORAGE ADDRESS CONFIGURATION TABLE 失效
标题翻译：使用单个存储地址配置表跟踪动态内存重新安装
公开(公告)号：US20110320755A1
公开(公告)日：2011-12-29
申请号：US12821986
申请日：2010-06-23
申请人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
发明人： Michael A. Blake , Pak-kin Mak , Michael F. Fee , Mark S. Farrell
IPC分类号： G06F12/06
CPC分类号： G06F12/0292
摘要： Tracking dynamic memory de-allocation using a single configuration table having a first register and a second register includes setting the first register as an active register, initiating a de-allocation of desired storage increments from a memory partition, setting the storage increments in the second register as invalid, purging all caches associated with the single configuration table, setting the second register as the active register and the first register as an inactive register, setting the desired storage increments in the first register as invalid, switching the active register from the second register to the first register to complete memory de-allocation using the single configuration table.
摘要翻译：使用具有第一寄存器和第二寄存器的单个配置表来跟踪动态存储器去分配包括将第一寄存器设置为活动寄存器，启动从存储器分区的期望存储增量的去分配，在第二寄存器中设置存储增量注册为无效，清除与单个配置表相关联的所有高速缓存，将第二个寄存器设置为活动寄存器，将第一个寄存器设置为非活动寄存器，将第一个寄存器中的所需存储增量设置为无效，将活动寄存器从第二个注册到第一个寄存器，使用单个配置表完成内存取消分配。

26. 发明申请

US20110314228A1 Maintaining Cache Coherence In A Multi-Node, Symmetric Multiprocessing Computer 失效
标题翻译：维持多节点对称多处理计算机中的缓存一致性
公开(公告)号：US20110314228A1
公开(公告)日：2011-12-22
申请号：US12816464
申请日：2010-06-16
申请人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Garrett M. Drapala , Pak-Kin Mak , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0833
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other compute nodes to all other nodes the state of the cache line on that node, including transmitting from any compute node having a correct copy to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译：在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由第一计算节点对高速缓存未命中的高速缓存行的请求进行广播; 从每个其他计算节点向所有其他节点传送该节点上的高速缓存行的状态，包括从具有正确副本的任何计算节点向第一节点发送正确的高速缓存行副本; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。

27. 发明申请

US20110314227A1 Horizontal Cache Persistence In A Multi-Compute Node, Symmetric Multiprocessing Computer 失效
标题翻译：多计算节点中的水平缓存持久性，对称多处理计算机
公开(公告)号：US20110314227A1
公开(公告)日：2011-12-22
申请号：US12819348
申请日：2010-06-21
申请人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski, JR. , Craig R. Walters
发明人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski, JR. , Craig R. Walters
IPC分类号： G06F12/08
CPC分类号： G06F12/127 , G06F12/084
摘要： Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.
摘要翻译：包括在多计算节点SMP计算机中的水平缓存持续性，包括响应于在计算节点的第一个计算节点上驱逐高速缓存行的确定，由第一计算节点广播高速缓存行的逐出通知; 发送接收计算节点的高速缓存行的状态，包括如果高速缓存线从计算节点丢失，则指示该计算节点是否具有可用于高速缓存行的高速缓存存储空间; 由所述第一计算节点根据所述高速缓存行的状态和可用空间来确定所述第一计算节点是否可以驱逐所述高速缓存行而不将高速缓存行写入主存储器; 并且根据所有计算节点中的高速缓存行的一个或多个状态，由每个计算节点更新每个计算节点中的高速缓存行的状态。

28. 发明申请

US20090210629A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SELECTIVELY PURGING CACHE ENTRIES 审中-公开
标题翻译：方法，系统和计算机程序产品，用于选择高速缓存进入
公开(公告)号：US20090210629A1
公开(公告)日：2009-08-20
申请号：US12032058
申请日：2008-02-15
申请人： Michael A. Blake , Christine C. Jones , Pak-kin Mak , Arthur J. O'Neill, JR.
发明人： Michael A. Blake , Christine C. Jones , Pak-kin Mak , Arthur J. O'Neill, JR.
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： A method, system and computer program product for selectively purging entries in a cache of a computer system. The method includes determining a starting storage address and a length of the storage address range to be purged, determining preset values for a congruence class and a compartment of a cache directory, accessing the cache directory based on the preset value of the congruence class, and selecting an entry in the cache directory based on the preset value of the compartment, determining validity of the entry accessed by examining an ownership tag of the entry, comparing a line address of the entry with the starting storage address and a sum of the starting storage address and the length of the storage address range, and selectively purging the entry based on the comparison result.
摘要翻译：一种用于选择性地清除计算机系统的高速缓存中的条目的方法，系统和计算机程序产品。该方法包括确定要清除的存储地址范围的起始存储地址和长度，确定高速缓存目录的同余类和隔间的预设值，基于同余类的预设值访问高速缓存目录;以及基于所述隔室的所述预设值来选择所述缓存目录中的条目，通过检查所述条目的所有权标签来确定所访问的条目的有效性，将所述条目的行地址与所述起始存储地址进行比较，以及所述起始存储器地址和存储地址范围的长度，并且基于比较结果选择性地清除条目。

29. 发明申请

US20080320226A1 Apparatus and Method for Improved Data Persistence within a Multi-node System 有权
标题翻译：在多节点系统内改善数据持久性的装置和方法
公开(公告)号：US20080320226A1
公开(公告)日：2008-12-25
申请号：US11766977
申请日：2007-06-22
申请人： Michael A. Blake , Harmony L. Helterhoff , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Harmony L. Helterhoff , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F12/0897 , G06F12/126
摘要： Improved access to retained data useful to a system is accomplished by managing data flow through cache associated with the processor(s) of a multi-node system. A data management facility operable with the processors and memory array directs the flow of data from the processors to the memory array by determining the path along which data evicted from a level of cache close to one of the processors is to return to a main memory and directing evicted data to be stored, if possible, in a horizontally associated cache.
摘要翻译：改进对对系统有用的保留数据的访问通过管理与多节点系统的处理器相关联的缓存的数据流来实现。可与处理器和存储器阵列一起操作的数据管理设备通过确定沿着哪个数据从处理器中的一个接收到的高速缓存驱逐出的数据返回到主存储器，从而将来自处理器的数据流引导到存储器阵列，如果可能的话，将被驱逐的数据存储在水平相关的缓存中。

30. 发明申请

US20080071990A1 Method for Ensuring Fairness Among Requests Within a Multi-Node Computer System 有权
标题翻译：确保多节点计算机系统内的请求之间公平的方法
公开(公告)号：US20080071990A1
公开(公告)日：2008-03-20
申请号：US11532156
申请日：2006-09-15
申请人： Craig R Walters , Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak
发明人： Craig R Walters , Vesselina K. Papazova , Michael A. Blake , Pak-kin Mak
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0815
摘要： A method to use of dual valid bit sets including a regular bit set and alternate valid bits set which prevents new requests to a given cache line from entering a multi-nodal computer systems' nest system until all requests to the given cache line have been completed successfully. By providing the alternate valid bits the dual set of resource valids for each remote requester is provided for each remote requester, where one set of valids indicates if the resource is valid and actively working on the line, and the other set of valids indicates if the resource was valid but encountered some conflict that requires resolution before the request can complete. Only on successful reload and completion of the remote operation does this alternate address valid bit reset and open the way for any pending interface requests to proceed, so all outstanding requests currently loaded in a local resource within the nest system are able to complete before new interface requests are allowed into the system.
摘要翻译：使用包括常规位集合和备用有效位集合的双重有效位集合的方法，其阻止对给定高速缓存行的新请求进入多节点计算机系统的嵌套系统，直到对给定高速缓存行的所有请求已经完成为止成功了通过提供替代的有效位，为每个远程请求者提供用于每个远程请求者的两组资源代码，其中一组代码指示资源是否有效并且在该行上主动地工作，而另一组代码指示是否资源有效，但在请求完成之前遇到一些需要解决的冲突。只有在成功重新加载和完成远程操作时，这个备用地址有效位复位，并为任何待处理的接口请求继续进行打开方式，因此当前加载到嵌套系统中的本地资源的所有未完成的请求都可以在新界面之前完成请求被允许进入系统。

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